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Commit 3c93ff4e authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Greg Kroah-Hartman
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x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value 



commit caa0ff24d5d0e02abce5e65c3d2b7f20a6617be5 upstream.

Due to TIF_SSBD and TIF_SPEC_IB the actual IA32_SPEC_CTRL value can
differ from x86_spec_ctrl_base. As such, keep a per-CPU value
reflecting the current task's MSR content.

  [jpoimboe: rename]

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarJosh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThadeu Lima de Souza Cascardo <cascardo@canonical.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9a596426

arch/x86/include/asm/nospec-branch.h

+1 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ static inline void indirect_branch_prediction_barrier(void) 


/* The Intel SPEC CTRL MSR base value cache */

extern u64 x86_spec_ctrl_base;

extern void write_spec_ctrl_current(u64 val);



/*

 * With retpoline, we must use IBRS to restrict branch prediction

arch/x86/kernel/cpu/bugs.c

+23 −5
Original line number Diff line number Diff line
@@ -47,11 +47,29 @@ static void __init taa_select_mitigation(void); 
static void __init mmio_select_mitigation(void);

static void __init srbds_select_mitigation(void);



/* The base value of the SPEC_CTRL MSR that always has to be preserved. */

/* The base value of the SPEC_CTRL MSR without task-specific bits set */

u64 x86_spec_ctrl_base;

EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);



/* The current value of the SPEC_CTRL MSR with task-specific bits set */

DEFINE_PER_CPU(u64, x86_spec_ctrl_current);

EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);



static DEFINE_MUTEX(spec_ctrl_mutex);



/*

 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ

 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().

 */

void write_spec_ctrl_current(u64 val)

{

	if (this_cpu_read(x86_spec_ctrl_current) == val)

		return;



	this_cpu_write(x86_spec_ctrl_current, val);

	wrmsrl(MSR_IA32_SPEC_CTRL, val);

}



/*

 * The vendor and possibly platform specific bits which can be modified in

 * x86_spec_ctrl_base.
@@ -1177,7 +1195,7 @@ static void __init spectre_v2_select_mitigation(void) 
	if (spectre_v2_in_eibrs_mode(mode)) {

		/* Force it so VMEXIT will restore correctly */

		x86_spec_ctrl_base |= SPEC_CTRL_IBRS;

		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

		write_spec_ctrl_current(x86_spec_ctrl_base);

	}



	switch (mode) {
@@ -1232,7 +1250,7 @@ static void __init spectre_v2_select_mitigation(void) 


static void update_stibp_msr(void * __unused)

{

	wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

	write_spec_ctrl_current(x86_spec_ctrl_base);

}



/* Update x86_spec_ctrl_base in case SMT state changed. */
@@ -1475,7 +1493,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) 
			x86_amd_ssb_disable();

		} else {

			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;

			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

			write_spec_ctrl_current(x86_spec_ctrl_base);

		}

	}
@@ -1692,7 +1710,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 
void x86_spec_ctrl_setup_ap(void)

{

	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))

		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

		write_spec_ctrl_current(x86_spec_ctrl_base);



	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)

		x86_amd_ssb_disable();

arch/x86/kernel/process.c

+1 −1
Original line number Diff line number Diff line
@@ -449,7 +449,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, 
	}



	if (updmsr)

		wrmsrl(MSR_IA32_SPEC_CTRL, msr);

		write_spec_ctrl_current(msr);

}



static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)