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Commit 3c5b9fce authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-alpha-pll: Add support for Lucid PLL print registers 



Lucid/Lucid5LPE PLL print registers are required to get the PLL values
from the debugfs, thus add support for the same.

Change-Id: I3a9eac33c80a98a0e612d9c7f740067aa54bde44
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent b38b5109

drivers/clk/qcom/clk-alpha-pll.c

+64 −0
Original line number Diff line number Diff line
@@ -2525,6 +2525,64 @@ static int alpha_pll_lucid_is_enabled(struct clk_hw *hw) 
	return lucid_pll_is_enabled(pll, pll->clkr.regmap);

}



static void lucid_pll_list_registers(struct seq_file *f,

		struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},

		{"PLL_USER_CTL_U1", PLL_OFF_USER_CTL_U1},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},

		{"PLL_STATUS", PLL_OFF_STATUS},

		{"PLL_OPMODE", PLL_OFF_OPMODE},

		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[0].offset], &val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

					data1[0].offset, &val);

		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);

	}

}



static struct clk_regmap_ops clk_lucid_pll_regmap_ops = {

	.list_registers = &lucid_pll_list_registers,

};



static void clk_lucid_pll_init(struct clk_hw *hw)

{

	struct clk_regmap *rclk = to_clk_regmap(hw);



	if (!rclk->ops)

		rclk->ops = &clk_lucid_pll_regmap_ops;

}



const struct clk_ops clk_alpha_pll_lucid_ops = {

	.prepare = alpha_pll_lucid_prepare,

	.unprepare = clk_unprepare_regmap,
@@ -2536,6 +2594,8 @@ const struct clk_ops clk_alpha_pll_lucid_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2554,6 +2614,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_5lpe_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2570,6 +2631,8 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { 
	.is_enabled = alpha_pll_lucid_is_enabled,

	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2594,6 +2657,7 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

drivers/clk/qcom/clk-alpha-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ enum { 
};



enum {

	PLL_OFF_MODE,

	PLL_OFF_L_VAL,

	PLL_OFF_CAL_L_VAL,

	PLL_OFF_ALPHA_VAL,