ARM: dts: msm: Add the lahaina gpu dtsi

#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

&soc {

	pil_gpu: qcom,kgsl-hyp {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a660_zap";

		memory-region = <&pil_gpu_mem>;

	};

	msm_gpu: qcom,kgsl-3d0@3d00000 {

		compatible = "qcom,kgsl-3d0";

		status = "ok";

		reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,

			<0x3de0000 0x10000>, <0x3d8b000 0x2000>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",

			"isense_cntl";

		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,chipid = <0x06060000>;

		qcom,initial-pwrlevel = <2>;

		qcom,no-nap;

		qcom,highest-bank-bit = <16>;

		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <4>;

		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */

		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;

		interconntect-names = "gpu_icc_path";

		qcom,bus-table-ddr7 =

			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */

			<MHZ_TO_KBPS(200, 4)>,  /* index=1  */

			<MHZ_TO_KBPS(451, 4)>,  /* index=2  */

			<MHZ_TO_KBPS(547, 4)>,  /* index=3  */

			<MHZ_TO_KBPS(681, 4)>,  /* index=4  */

			<MHZ_TO_KBPS(768, 4)>,  /* index=5  */

			<MHZ_TO_KBPS(1017, 4)>, /* index=6  */

			<MHZ_TO_KBPS(1353, 4)>, /* index=7  */

			<MHZ_TO_KBPS(1555, 4)>, /* index=8  */

			<MHZ_TO_KBPS(1708, 4)>, /* index=9  */

			<MHZ_TO_KBPS(2092, 4)>; /* index=10  */

		qcom,bus-table-ddr8 =

			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */

			<MHZ_TO_KBPS(200, 4)>,  /* index=1  */

			<MHZ_TO_KBPS(451, 4)>,  /* index=2  */

			<MHZ_TO_KBPS(547, 4)>,  /* index=3  */

			<MHZ_TO_KBPS(681, 4)>,  /* index=4  */

			<MHZ_TO_KBPS(768, 4)>,  /* index=5  */

			<MHZ_TO_KBPS(1017, 4)>, /* index=6  */

			<MHZ_TO_KBPS(1555, 4)>, /* index=7  */

			<MHZ_TO_KBPS(1708, 4)>, /* index=8  */

			<MHZ_TO_KBPS(2092, 4)>, /* index=9  */

			<MHZ_TO_KBPS(2736, 4)>, /* index=10  */

			<MHZ_TO_KBPS(3196, 4)>; /* index=11  */

		qcom,bus-table-cnoc =

			<0>,   /* Off */

			<100>; /* On */

		qcom,gpu-mempools {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";

			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

				qcom,mempool-reserved = <2048>;

				qcom,mempool-allocate;

			};

			/* 8K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <8192>;

				qcom,mempool-reserved = <1024>;

				qcom,mempool-allocate;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@2 {

				reg = <2>;

				qcom,mempool-page-size = <65536>;

				qcom,mempool-reserved = <256>;

			};

			/* 1M Page Pool configuration */

			qcom,gpu-mempool@3 {

				reg = <3>;

				qcom,mempool-page-size = <1048576>;

				qcom,mempool-reserved = <32>;

			};

		};

		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <540000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <1>;

				qcom,bus-min = <1>;

				qcom,bus-max = <1>;

			};

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <443000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <1>;

				qcom,bus-min = <1>;

				qcom,bus-max = <1>;

			};

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <315000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

				qcom,bus-freq = <1>;

				qcom,bus-min = <1>;

				qcom,bus-max = <1>;

			};

		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x03da0000 0x20000>;

		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

			<&clock_gpucc GPU_CC_AHB_CLK>;

		clock-names = "gcc_gpu_memnoc_gfx",

				"gcc_gpu_snoc_dvm_gfx",

				"gpu_cc_ahb";

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 0x0 0x400>;

			qcom,iommu-dma = "disabled";

		};

		gfx3d_lpac: gfx3d_lpac {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 0x1 0x400>;

			qcom,iommu-dma = "disabled";

		};

		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 0x2 0x400>;

			qcom,iommu-dma = "disabled";

		};

	};

	gmu: qcom,gmu@3d69000 {

		compatible = "qcom,gpu-gmu";

		reg = <0x3d6a000 0x30000>,

			<0xb290000 0x10000>;

		reg-names = "kgsl_gmu_reg",

			"kgsl_gmu_pdc_cfg";

		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,

			<0 305 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";

		regulator-names = "vddcx", "vdd";

		vddcx-supply = <&gpu_cc_cx_gdsc>;

		vdd-supply = <&gpu_cc_gx_gdsc>;

		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,

			<&clock_gpucc GPU_CC_CXO_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&clock_gpucc GPU_CC_AHB_CLK>,

			<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>;

		clock-names = "gmu_clk", "cxo_clk", "axi_clk",

			"memnoc_clk", "ahb_clk", "hub_clk";

		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";

		gmu_user: gmu_user {

			compatible = "qcom,smmu-gmu-user-cb";

			iommus = <&kgsl_smmu 0x4 0x400>;

			qcom,iommu-dma = "disabled";

		};

		gmu_kernel: gmu_kernel {

			compatible = "qcom,smmu-gmu-kernel-cb";

			iommus = <&kgsl_smmu 0x5 0x400>;

			qcom,iommu-dma = "disabled";

		};

	};

};

#include "lahaina-vidc.dtsi"

#include "lahaina-vidc.dtsi"

#include "lahaina-cvp.dtsi"

#include "lahaina-cvp.dtsi"

#include "lahaina-pcie.dtsi"

#include "lahaina-pcie.dtsi"

#include "lahaina-gpu.dtsi"