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Commit 3c23ed13 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by Jani Nikula
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drm/i915: Fix the pipe state timing mismatch warnings 



Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.

v2: Use the existing intel_get_pipe_timings and do the dsi
    specific adjustments in the encoder get_config hook.(Ville, Jani)

v3: Exclude VBLANK and HBLANK registers for dsi transcoder.

v4: Fix the incomplete conditional logic.

Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-1-git-send-email-vandita.kulkarni@intel.com
parent cdd07596

drivers/gpu/drm/i915/icl_dsi.c

+28 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,33 @@ static void gen11_dsi_disable(struct intel_encoder *encoder, 
	gen11_dsi_disable_io_power(encoder);

}



static void gen11_dsi_get_timings(struct intel_encoder *encoder,

				  struct intel_crtc_state *pipe_config)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	struct drm_display_mode *adjusted_mode =

					&pipe_config->base.adjusted_mode;



	if (intel_dsi->dual_link) {

		adjusted_mode->crtc_hdisplay *= 2;

		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)

			adjusted_mode->crtc_hdisplay -=

						intel_dsi->pixel_overlap;

		adjusted_mode->crtc_htotal *= 2;

	}

	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;

	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;



	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {

		if (intel_dsi->dual_link) {

			adjusted_mode->crtc_hsync_start *= 2;

			adjusted_mode->crtc_hsync_end *= 2;

		}

	}

	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;

	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;

}



static void gen11_dsi_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_state *pipe_config)

{
@@ -1185,6 +1212,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, 
	pipe_config->port_clock =

		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);

	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;

	gen11_dsi_get_timings(encoder, pipe_config);

	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);

}

drivers/gpu/drm/i915/intel_display.c

+16 −6
Original line number Diff line number Diff line
@@ -7750,9 +7750,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, 
	tmp = I915_READ(HTOTAL(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;



	if (!transcoder_is_dsi(cpu_transcoder)) {

		tmp = I915_READ(HBLANK(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;

		pipe_config->base.adjusted_mode.crtc_hblank_start =

							(tmp & 0xffff) + 1;

		pipe_config->base.adjusted_mode.crtc_hblank_end =

						((tmp >> 16) & 0xffff) + 1;

	}

	tmp = I915_READ(HSYNC(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
@@ -7760,9 +7765,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, 
	tmp = I915_READ(VTOTAL(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;



	if (!transcoder_is_dsi(cpu_transcoder)) {

		tmp = I915_READ(VBLANK(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;

		pipe_config->base.adjusted_mode.crtc_vblank_start =

							(tmp & 0xffff) + 1;

		pipe_config->base.adjusted_mode.crtc_vblank_end =

						((tmp >> 16) & 0xffff) + 1;

	}

	tmp = I915_READ(VSYNC(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;