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Commit 3c23a7b8 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0/gr: add support for nvcf chipset 



untested, written from a trace, accel disabled by default until it is

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a12036ba

drivers/gpu/drm/nouveau/nouveau_state.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1011,6 +1011,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) 
		switch (dev_priv->chipset) {

		switch (dev_priv->chipset) {

		case 0xc1: /* known broken */

		case 0xc1: /* known broken */

		case 0xc8: /* never tested */

		case 0xc8: /* never tested */

		case 0xcf: /* never tested */

			NV_INFO(dev, "acceleration disabled by default, pass "

			NV_INFO(dev, "acceleration disabled by default, pass "

				     "noaccel=0 to force enable\n");

				     "noaccel=0 to force enable\n");

			dev_priv->noaccel = true;

			dev_priv->noaccel = true;

drivers/gpu/drm/nouveau/nvc0_graph.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -864,6 +864,9 @@ nvc0_graph_create(struct drm_device *dev) 
	case 0xce: /* 4/4/0/0, 4 */

	case 0xce: /* 4/4/0/0, 4 */

		priv->magic_not_rop_nr = 0x03;

		priv->magic_not_rop_nr = 0x03;

		break;

		break;

	case 0xcf: /* 4/0/0/0, 3 */

		priv->magic_not_rop_nr = 0x03;

		break;

	}

	}





	if (!priv->magic_not_rop_nr) {

	if (!priv->magic_not_rop_nr) {

drivers/gpu/drm/nouveau/nvc0_graph.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -82,6 +82,7 @@ nvc0_graph_class(struct drm_device *dev) 
	case 0xc3:

	case 0xc3:

	case 0xc4:

	case 0xc4:

	case 0xce: /* guess, mmio trace shows only 0x9097 state */

	case 0xce: /* guess, mmio trace shows only 0x9097 state */

	case 0xcf: /* guess, mmio trace shows only 0x9097 state */

		return 0x9097;

		return 0x9097;

	case 0xc1:

	case 0xc1:

		return 0x9197;

		return 0x9197;

drivers/gpu/drm/nouveau/nvc0_grctx.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -1678,7 +1678,10 @@ nvc0_grctx_generate_tp(struct drm_device *dev) 
	nv_wr32(dev, 0x419c04, 0x00000006);

	nv_wr32(dev, 0x419c04, 0x00000006);

	nv_wr32(dev, 0x419c08, 0x00000002);

	nv_wr32(dev, 0x419c08, 0x00000002);

	nv_wr32(dev, 0x419c20, 0x00000000);

	nv_wr32(dev, 0x419c20, 0x00000000);

	nv_wr32(dev, 0x419cb0, 0x00060048); //XXX: 0xce 0x00020048

	if (chipset == 0xce || chipset == 0xcf)

		nv_wr32(dev, 0x419cb0, 0x00020048);

	else

		nv_wr32(dev, 0x419cb0, 0x00060048);

	nv_wr32(dev, 0x419ce8, 0x00000000);

	nv_wr32(dev, 0x419ce8, 0x00000000);

	nv_wr32(dev, 0x419cf4, 0x00000183);

	nv_wr32(dev, 0x419cf4, 0x00000183);

	nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000);

	nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000);
@@ -1784,7 +1787,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan) 




	if (1) {

	if (1) {

		const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0,

		const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0,

					      16, 0, 0, 0, 0, 0, 8, 0 };

					      16, 0, 0, 0, 0, 0, 8, 4 };

		u8 max = chipset_tp_max[dev_priv->chipset & 0x0f];

		u8 max = chipset_tp_max[dev_priv->chipset & 0x0f];

		u8 tpnr[GPC_MAX];

		u8 tpnr[GPC_MAX];

		u8 data[TP_MAX];

		u8 data[TP_MAX];

drivers/gpu/drm/nouveau/nvc0_grgpc.fuc

+7 −1
Original line number Original line Diff line number Diff line
@@ -77,6 +77,11 @@ chipsets: 
.b16 nvc0_gpc_mmio_tail

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc0_tpc_mmio_head

.b16 nvc3_tpc_mmio_tail

.b16 nvc3_tpc_mmio_tail

.b8  0xcf 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvcf_tpc_mmio_tail

.b8  0 0 0 0

.b8  0 0 0 0





// GPC mmio lists

// GPC mmio lists
@@ -134,8 +139,9 @@ mmctx_data(0x000750, 2) 
nvc0_tpc_mmio_tail:

nvc0_tpc_mmio_tail:

mmctx_data(0x000758, 1)

mmctx_data(0x000758, 1)

mmctx_data(0x0002c4, 1)

mmctx_data(0x0002c4, 1)

mmctx_data(0x0004bc, 1)

mmctx_data(0x0006e0, 1)

mmctx_data(0x0006e0, 1)

nvcf_tpc_mmio_tail:

mmctx_data(0x0004bc, 1)

nvc3_tpc_mmio_tail:

nvc3_tpc_mmio_tail:

mmctx_data(0x000544, 1)

mmctx_data(0x000544, 1)

nvc1_tpc_mmio_tail:

nvc1_tpc_mmio_tail: