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Commit 3bcf603f authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
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drm/i915: apply timing generator bug workaround on CPT and PPT 



On CougarPoint and PantherPoint PCH chips, the timing generator may fail
to start after DP training completes.  This is due to a bug in the
FDI autotraining detect logic (which will stall the timing generator and
re-enable it once training completes), so disable it to avoid silent DP
mode setting failures.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 120eced9

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -3072,6 +3072,11 @@ 
#define  TRANS_6BPC             (2<<5)

#define  TRANS_12BPC            (3<<5)



#define _TRANSA_CHICKEN2	 0xf0064

#define _TRANSB_CHICKEN2	 0xf1064

#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)



#define SOUTH_CHICKEN2		0xc2004

#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)

drivers/gpu/drm/i915/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -7524,6 +7524,7 @@ static void ibx_init_clock_gating(struct drm_device *dev) 
static void cpt_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock
@@ -7533,6 +7534,9 @@ static void cpt_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

		   DPLS_EDP_PPS_FIX_DIS);

	/* Without this, mode sets may fail silently on FDI */

	for_each_pipe(pipe)

		I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);

}



static void ironlake_teardown_rc6(struct drm_device *dev)