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Commit 3bb26006 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge tag 'perf-urgent-for-mingo-5.0-20190205' of...

Merge tag 'perf-urgent-for-mingo-5.0-20190205' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

 into perf/urgent

Pull perf/urgent fixes from Arnaldo Carvalho de Melo:

perf trace:

  Arnaldo Carvalho de Melo:

    Fix handling of probe:vfs_getname when the probed routine is
    inlined in multiple places, fixing the collection of the 'filename'
    parameter in open syscalls.

perf test:

  Gustavo A. R. Silva:

    Fix bitwise operator usage in evsel-tp-sched test, which made tat
    test always detect fields as signed.

  Jiri Olsa:

    Filter out hidden symbols from labels, added in systems where the
    annobin plugin is used, such as RHEL8, which, if left in place make
    the DWARF unwind 'perf test' to fail on PPC.

  Tony Jones:

    Fix 'perf_event_attr' tests when building with python3.

perf mem/c2c:

  Ravi Bangoria:

    Fix perf_mem_events on PowerPC.

tools headers UAPI:

  Arnaldo Carvalho de Melo:

    Sync linux/in.h copy from the kernel sources, silencing a perf build warning.

Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 9dff0aa9 8f2f350c
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+1 −1
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@@ -268,7 +268,7 @@ struct sockaddr_in {
#define	IN_MULTICAST(a)		IN_CLASSD(a)
#define	IN_MULTICAST_NET	0xe0000000

#define	IN_BADCLASS(a)		((((long int) (a) ) == 0xffffffff)
#define	IN_BADCLASS(a)		(((long int) (a) ) == (long int)0xffffffff)
#define	IN_EXPERIMENTAL(a)	IN_BADCLASS((a))

#define	IN_CLASSE(a)		((((long int) (a)) & 0xf0000000) == 0xf0000000)
+12 −4
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@@ -19,8 +19,11 @@ C2C stands for Cache To Cache.
The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
you to track down the cacheline contentions.

The tool is based on x86's load latency and precise store facility events
provided by Intel CPUs. These events provide:
On x86, the tool is based on load latency and precise store facility events
provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
with thresholding feature.

These events provide:
  - memory address of the access
  - type of the access (load and store details)
  - latency (in cycles) of the load access
@@ -46,7 +49,7 @@ RECORD OPTIONS

-l::
--ldlat::
	Configure mem-loads latency.
	Configure mem-loads latency. (x86 only)

-k::
--all-kernel::
@@ -119,11 +122,16 @@ Following perf record options are configured by default:
  -W,-d,--phys-data,--sample-cpu

Unless specified otherwise with '-e' option, following events are monitored by
default:
default on x86:

  cpu/mem-loads,ldlat=30/P
  cpu/mem-stores/P

and following on PowerPC:

  cpu/mem-loads/
  cpu/mem-stores/

User can pass any 'perf record' option behind '--' mark, like (to enable
callchains and system wide monitoring):

+1 −1
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@@ -82,7 +82,7 @@ RECORD OPTIONS
	Be more verbose (show counter open errors, etc)

--ldlat <n>::
	Specify desired latency for loads event.
	Specify desired latency for loads event. (x86 only)

In addition, for report all perf report options are valid, and for record
all perf record options.
+1 −0
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@@ -2,6 +2,7 @@ libperf-y += header.o
libperf-y += sym-handling.o
libperf-y += kvm-stat.o
libperf-y += perf_regs.o
libperf-y += mem-events.o

libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_DWARF) += skip-callchain-idx.o
+11 −0
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// SPDX-License-Identifier: GPL-2.0
#include "mem-events.h"

/* PowerPC does not support 'ldlat' parameter. */
char *perf_mem_events__name(int i)
{
	if (i == PERF_MEM_EVENTS__LOAD)
		return (char *) "cpu/mem-loads/";

	return (char *) "cpu/mem-stores/";
}
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