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Commit 3bb11b53 authored by Sonika Jindal's avatar Sonika Jindal Committed by Daniel Vetter
Browse files

drm/i915: Continuation of future readiness series 



Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
platforms are checked separately.

v2: Reordering as per the gen (Ville)

Signed-off-by: default avatarSonika Jindal <sonika.jindal@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 22c59960

drivers/gpu/drm/i915/intel_display.c

+20 −22
Original line number Original line Diff line number Diff line
@@ -12354,8 +12354,9 @@ static void intel_init_display(struct drm_device *dev) 
		dev_priv->display.get_display_clock_speed =

		dev_priv->display.get_display_clock_speed =

			i830_get_display_clock_speed;

			i830_get_display_clock_speed;





	if (HAS_PCH_SPLIT(dev)) {

	if (IS_G4X(dev)) {

		if (IS_GEN5(dev)) {

		dev_priv->display.write_eld = g4x_write_eld;

	} else if (IS_GEN5(dev)) {

		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

		dev_priv->display.write_eld = ironlake_write_eld;

		dev_priv->display.write_eld = ironlake_write_eld;

	} else if (IS_GEN6(dev)) {

	} else if (IS_GEN6(dev)) {
@@ -12374,9 +12375,6 @@ static void intel_init_display(struct drm_device *dev) 
		dev_priv->display.write_eld = haswell_write_eld;

		dev_priv->display.write_eld = haswell_write_eld;

		dev_priv->display.modeset_global_resources =

		dev_priv->display.modeset_global_resources =

			haswell_modeset_global_resources;

			haswell_modeset_global_resources;

		}

	} else if (IS_G4X(dev)) {

		dev_priv->display.write_eld = g4x_write_eld;

	} else if (IS_VALLEYVIEW(dev)) {

	} else if (IS_VALLEYVIEW(dev)) {

		dev_priv->display.modeset_global_resources =

		dev_priv->display.modeset_global_resources =

			valleyview_modeset_global_resources;

			valleyview_modeset_global_resources;