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Commit 3b4c0988 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: clk-alpha-pll: Add support for Lucid EVO PLL 



Lucid EVO PLL is required to be supported from HLOS clock
controller, thus add support for lucid evo pll ops.

Change-Id: Iccd5884e0298fabba028bd4e2e3e22c3faca024c
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent 5ae51bab

drivers/clk/qcom/clk-alpha-pll.c

+209 −0
Original line number Diff line number Diff line
@@ -257,8 +257,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define LUCID_5LPE_ENABLE_VOTE_RUN	BIT(21)

#define LUCID_5LPE_PLL_LATCH_INPUT	BIT(14)

#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH	BIT(13)

#define LUCID_EVO_PCAL_NOT_DONE		BIT(8)

#define LUCID_EVO_ENABLE_VOTE_RUN	BIT(25)

#define LUCID_EVO_PLL_L_VAL_MASK	GENMASK(15, 0)

#define LUCID_EVO_PLL_CAL_L_VAL_MASK	GENMASK(31, 16)



/* ZONDA PLL specific offsets */

#define ZONDA_PLL_OUT_MASK		0xF
@@ -3216,6 +3218,79 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 
};

EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);



int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,

		struct regmap *regmap, const struct alpha_pll_config *config)

{

	int ret;



	ret = lucid_pll_is_enabled(pll, regmap);

	if (ret)

		return ret;



	if (config->l)

		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),

					LUCID_EVO_PLL_L_VAL_MASK, config->l);



	if (config->cal_l)

		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),

				LUCID_EVO_PLL_CAL_L_VAL_MASK, config->cal_l);

	else

		ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),

			LUCID_EVO_PLL_CAL_L_VAL_MASK, LUCID_PLL_CAL_VAL);



	if (config->alpha)

		ret |= regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);



	if (config->config_ctl_val)

		ret |= regmap_write(regmap, PLL_CONFIG_CTL(pll),

				config->config_ctl_val);



	if (config->config_ctl_hi_val)

		ret |= regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

				config->config_ctl_hi_val);



	if (config->config_ctl_hi1_val)

		ret |= regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),

				config->config_ctl_hi1_val);



	if (config->user_ctl_val)

		ret |= regmap_write(regmap, PLL_USER_CTL(pll),

				config->user_ctl_val);



	if (config->user_ctl_hi_val)

		ret |= regmap_write(regmap, PLL_USER_CTL_U(pll),

				config->user_ctl_hi_val);



	if (config->test_ctl_val)

		ret |= regmap_write(regmap, PLL_TEST_CTL(pll),

				config->test_ctl_val);



	if (config->test_ctl_hi_val)

		ret |= regmap_write(regmap, PLL_TEST_CTL_U(pll),

				config->test_ctl_hi_val);



	if (config->test_ctl_hi1_val)

		ret |= regmap_write(regmap, PLL_TEST_CTL_U1(pll),

				config->test_ctl_hi1_val);



	/* Disable PLL output */

	ret |= regmap_update_bits(regmap, PLL_MODE(pll),

					PLL_OUTCTRL, 0);



	/* Set operation mode to STANDBY */

	ret |= regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);



	/* PLL should be in OFF mode before continuing */

	wmb();



	/* Place the PLL in STANDBY mode */

	ret |= regmap_update_bits(regmap, PLL_MODE(pll),

				 PLL_RESET_N, PLL_RESET_N);



	return ret ? -EIO : 0;

}

EXPORT_SYMBOL(clk_lucid_evo_pll_configure);



static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -3306,6 +3381,67 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 
			PLL_OPMODE_STANDBY);

}



/*

 * The Lucid PLL requires a power-on self-calibration which happens when the

 * PLL comes out of reset. The calibration is performed at an output frequency

 * of ~1300 MHz which means that SW will have to vote on a voltage that's

 * equal to or greater than SVS_L1 on the corresponding rail. Since this is not

 * feasable to do in the atomic enable path, temporarily bring up the PLL here,

 * let it calibrate, and place it in standby before returning.

 */

static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	struct clk_hw *p;

	u32 regval;

	unsigned long prate;

	int ret;



	ret = clk_prepare_regmap(hw);

	if (ret)

		return ret;



	/* Return early if calibration is not needed. */

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (!(regval & LUCID_EVO_PCAL_NOT_DONE))

		return 0;



	if (pll->config) {

		/*

		 * Reconfigure the PLL if CAL_L_VAL is 0 (which implies that all

		 * clock controller registers have been reset).

		 */

		regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &regval);

		regval &= LUCID_EVO_PLL_CAL_L_VAL_MASK;

		if (!regval) {

			pr_debug("reconfiguring %s after it was reset\n",

				clk_hw_get_name(hw));

			ret = clk_lucid_evo_pll_configure(pll,

				pll->clkr.regmap, pll->config);

			if (ret) {

				pr_err("pll configuration failed: %u\n", ret);

				return ret;

			}

		}

	}



	p = clk_hw_get_parent(hw);

	if (!p)

		return -EINVAL;



	prate = clk_hw_get_rate(p);

	if (!prate)

		return -EINVAL;



	ret = alpha_pll_lucid_evo_enable(hw);

	if (ret)

		return ret;



	alpha_pll_lucid_evo_disable(hw);



	return 0;

}



static unsigned long

alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{
@@ -3354,6 +3490,60 @@ static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, 
				val << pll->post_div_shift);

}



static int alpha_pll_lucid_evo_set_rate(struct clk_hw *hw, unsigned long rate,

					unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 regval, l;

	u64 a;

	int ret;



	rrate = alpha_pll_round_rate(rate, prate, &l, &a,

					ALPHA_REG_16BIT_WIDTH);

	/*

	 * Due to a limited number of bits for fractional rate programming, the

	 * rounded up rate could be marginally higher than the requested rate.

	 */

	if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) {

		pr_err("Call set rate on the PLL with rounded rates!\n");

		return -EINVAL;

	}



	regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll),

			   LUCID_EVO_PLL_L_VAL_MASK, l);

	regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll),

			   LUCID_EVO_PLL_CAL_L_VAL_MASK, a);



	/* Latch the PLL input */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

			LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT);

	if (ret)

		return ret;



	/* Wait for 2 reference cycles before checking the ACK bit. */

	udelay(1);

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) {

		WARN(1, "PLL latch failed. Output may be unstable!\n");

		return -EINVAL;

	}



	/* Return the latch input to 0 */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

			LUCID_5LPE_PLL_LATCH_INPUT, 0);

	if (ret)

		return ret;



	if (clk_hw_is_enabled(hw)) {

		ret = wait_for_pll_enable_lock(pll);

		if (ret)

			return ret;

	}



	return 0;

}



static void lucid_evo_pll_list_registers(struct seq_file *f,

		struct clk_hw *hw)

{
@@ -3434,6 +3624,25 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 
};

EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_evo_ops);



const struct clk_ops clk_alpha_pll_lucid_evo_ops = {

	.prepare = alpha_pll_lucid_evo_prepare,

	.unprepare = clk_unprepare_regmap,

	.pre_rate_change = clk_pre_change_regmap,

	.post_rate_change = clk_post_change_regmap,

	.enable = alpha_pll_lucid_evo_enable,

	.disable = alpha_pll_lucid_evo_disable,

	.is_enabled = alpha_pll_lucid_is_enabled,

	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_evo_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_evo_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

};

EXPORT_SYMBOL(clk_alpha_pll_lucid_evo_ops);



int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config)

{

drivers/clk/qcom/clk-alpha-pll.h

+4 −0
Original line number Diff line number Diff line
@@ -165,6 +165,7 @@ extern const struct clk_ops clk_agera_pll_ops; 


extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;

extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;

extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);
@@ -186,4 +187,7 @@ int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
				const struct alpha_pll_config *config);

int clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

					const struct alpha_pll_config *config);

int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,

				struct regmap *regmap,

				const struct alpha_pll_config *config);

#endif