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Unverified Commit 3b25b763 authored by Paul Cercueil's avatar Paul Cercueil Committed by Paul Burton
Browse files

MIPS: Rename JZRISC to XBURST 



The real name of the CPU present in the JZ line of SoCs from Ingenic is
XBurst, not JZRISC.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
[paul.burton@mips.com: Leave /proc/cpuinfo string as-is.]
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
parent 7176b6ac

arch/mips/include/asm/cpu-type.h

+1 −1
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \

    defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)

	case CPU_4KEC:

	case CPU_JZRISC:

	case CPU_XBURST:

#endif



#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2

arch/mips/include/asm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ 
 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*

 */



#define PRID_IMP_JZRISC	       0x0200

#define PRID_IMP_XBURST	       0x0200



/*

 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
@@ -315,7 +315,7 @@ enum cpu_type_enum { 
	 */

	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,

	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON1, CPU_M14KC,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,

	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,

arch/mips/kernel/cpu-probe.c

+3 −3
Original line number Diff line number Diff line
@@ -1956,12 +1956,12 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 
static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)

{

	decode_configs(c);

	/* JZRISC does not implement the CP0 counter. */

	/* XBurst does not implement the CP0 counter. */

	c->options &= ~MIPS_CPU_COUNTER;

	BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);

	switch (c->processor_id & PRID_IMP_MASK) {

	case PRID_IMP_JZRISC:

		c->cputype = CPU_JZRISC;

	case PRID_IMP_XBURST:

		c->cputype = CPU_XBURST;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		__cpu_name[cpu] = "Ingenic JZRISC";

		break;

arch/mips/kernel/idle.c

+1 −1
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ void __init check_wait(void) 
	case CPU_CAVIUM_OCTEON_PLUS:

	case CPU_CAVIUM_OCTEON2:

	case CPU_CAVIUM_OCTEON3:

	case CPU_JZRISC:

	case CPU_XBURST:

	case CPU_LOONGSON1:

	case CPU_XLR:

	case CPU_XLP:

arch/mips/mm/sc-mips.c

+1 −1
Original line number Diff line number Diff line
@@ -225,7 +225,7 @@ static inline int __init mips_sc_probe(void) 
	 * According to config2 it would be 5-ways, but that is contradicted

	 * by all documentation.

	 */

	if (current_cpu_type() == CPU_JZRISC &&

	if (current_cpu_type() == CPU_XBURST &&

				mips_machtype == MACH_INGENIC_JZ4770)

		c->scache.ways = 4;