spi: sifive: Add DT documentation for SiFive SPI controller

SiFive SPI controller Device Tree Bindings

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Required properties:

- compatible		: Should be "sifive,<chip>-spi" and "sifive,spi<version>".

			  Supported compatible strings are:

			  "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated

			  onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive

			  SPI v0 IP block with no chip integration tweaks.

			  Please refer to sifive-blocks-ip-versioning.txt for details

- reg			: Physical base address and size of SPI registers map

			  A second (optional) range can indicate memory mapped flash

- interrupts		: Must contain one entry

- interrupt-parent	: Must be core interrupt controller

- clocks		: Must reference the frequency given to the controller

- #address-cells	: Must be '1', indicating which CS to use

- #size-cells		: Must be '0'

Optional properties:

- sifive,fifo-depth		: Depth of hardware queues; defaults to 8

- sifive,max-bits-per-word	: Maximum bits per word; defaults to 8

SPI RTL that corresponds to the IP block version numbers can be found here:

https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi

Example:

	spi: spi@10040000 {

		compatible = "sifive,fu540-c000-spi", "sifive,spi0";

		reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;

		interrupt-parent = <&plic>;

		interrupts = <51>;

		clocks = <&tlclk>;

		#address-cells = <1>;

		#size-cells = <0>;

		sifive,fifo-depth = <8>;

		sifive,max-bits-per-word = <8>;

	};