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Commit 3aa04160 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Make switch out of secure more target specific 



The generic Adreno code was reaching into the a5xx specific code to
run the critical packets.  This is mostly unnecessary because the
a5xx code is the one that calls into the generic code in the first
place so it is a useless round trip especially for such simple
code. Move the secure switch code into the target specific code.

Change-Id: Ic0dedbadf6d25a0740719cf8ac0ccf8802f4c33e
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 6dfe8d81

drivers/gpu/msm/adreno.c

+1 −26
Original line number Diff line number Diff line
@@ -1822,7 +1822,7 @@ static void _set_secvid(struct kgsl_device *device) 
	}

}



static int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

				struct adreno_ringbuffer *rb)

{

	unsigned int *cmds;
@@ -1844,31 +1844,6 @@ static int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev, 
	return ret;

}



int adreno_set_unsecured_mode(struct adreno_device *adreno_dev,

		struct adreno_ringbuffer *rb)

{

	int ret = 0;



	if (!adreno_is_a5xx(adreno_dev) && !adreno_is_a6xx(adreno_dev))

		return -EINVAL;



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS) &&

			adreno_is_a5xx(adreno_dev)) {

		ret = a5xx_critical_packet_submit(adreno_dev, rb);

		if (ret)

			return ret;

	}



	/* GPU comes up in secured mode, make it unsecured by default */

	if (adreno_dev->zap_loaded)

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);

	else

		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TRUST_CONTROL, 0x0);



	return ret;

}



static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)

{

	int i;

drivers/gpu/msm/adreno.h

+11 −6
Original line number Diff line number Diff line
@@ -663,8 +663,6 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

	ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

	ADRENO_REG_RBBM_SECVID_TRUST_CONFIG,

	ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,
@@ -913,10 +911,17 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv, 
		unsigned int cmd, unsigned long arg,

		const struct kgsl_ioctl *cmds, int len);



int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

		struct adreno_ringbuffer *rb);

int adreno_set_unsecured_mode(struct adreno_device *adreno_dev,

/*

 * adreno_switch_to_unsecure_mode - Execute a zap shader

 * @adreno_dev: An Adreno GPU handle

 * @rb: The ringbuffer to execute on

 *

 * Execute the zap shader from the CP to take the GPU out of secure mode.

 * Return: 0 on success or negative on failure

 */

int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

				struct adreno_ringbuffer *rb);



void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str);

int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);

int adreno_idle(struct kgsl_device *device);

drivers/gpu/msm/adreno_a5xx.c

+17 −7
Original line number Diff line number Diff line
@@ -1811,7 +1811,7 @@ static void _set_ordinals(struct adreno_device *adreno_dev, 
		*cmds++ = 0x0;

}



int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,

					struct adreno_ringbuffer *rb)

{

	unsigned int *cmds;
@@ -1907,8 +1907,22 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev) 
	if (ret)

		return ret;



	/* GPU comes up in secured mode, make it unsecured by default */

	ret = adreno_set_unsecured_mode(adreno_dev, rb);

	/* Run the critical packets if we need to */

	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS)) {

		ret = a5xx_critical_packet_submit(adreno_dev, rb);

		if (ret)

			return ret;

	}



	/*

	 * Try to execute the zap shader if it exists, otherwise just try

	 * directly writing to the control register

	 */

	if (!adreno_dev->zap_loaded)

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0);

	else

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);



	if (ret)

		return ret;
@@ -2433,10 +2447,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A5XX_RBBM_PERFCTR_LOAD_VALUE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A5XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

				A5XX_RBBM_SECVID_TRUST_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONFIG,

				A5XX_RBBM_SECVID_TRUST_CONFIG),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

				A5XX_RBBM_SECVID_TSB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

drivers/gpu/msm/adreno_a6xx.c

+9 −4
Original line number Diff line number Diff line
@@ -816,8 +816,15 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev) 
	if (ret)

		return ret;



	/* GPU comes up in secured mode, make it unsecured by default */

	ret = adreno_set_unsecured_mode(adreno_dev, rb);

	/*

	 * Take the GPU out of secure mode. Try the zap shader if it is loaded,

	 * otherwise just try to write directly to the secure control register

	 */

	if (!adreno_dev->zap_loaded)

		kgsl_regwrite(device, A6XX_RBBM_SECVID_TRUST_CNTL, 0);

	else

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);



	if (ret)

		return ret;
@@ -2370,8 +2377,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A6XX_GMU_CM3_CFG),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,

				A6XX_GMU_RBBM_INT_UNMASKED_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,

				A6XX_RBBM_SECVID_TRUST_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

				A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,