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Commit 3a8b11f3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: add clk rpmh support for Kona"

parents e3438e35 dc97f082

drivers/clk/qcom/clk-rpmh.c

+62 −5
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -62,6 +62,7 @@ struct clk_rpmh { 
	struct clk_hw hw;

	const char *res_name;

	u8 div;

	bool optional;

	u32 res_addr;

	u32 res_on_val;

	u32 state;
@@ -81,13 +82,14 @@ struct clk_rpmh_desc { 
static DEFINE_MUTEX(rpmh_clk_lock);



#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  _res_en_offset, _res_on, _div)		\

			  _res_en_offset, _res_on, _div, _optional)	\

	static struct clk_rpmh _platform##_##_name_active;		\

	static struct clk_rpmh _platform##_##_name = {			\

		.res_name = _res_name,					\

		.res_addr = _res_en_offset,				\

		.res_on_val = _res_on,					\

		.div = _div,						\

		.optional = _optional,					\

		.peer = &_platform##_##_name_active,			\

		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\

				      BIT(RPMH_ACTIVE_ONLY_STATE) |	\
@@ -104,6 +106,7 @@ static DEFINE_MUTEX(rpmh_clk_lock); 
		.res_addr = _res_en_offset,				\

		.res_on_val = _res_on,					\

		.div = _div,						\

		.optional = _optional,					\

		.peer = &_platform##_##_name,				\

		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\

					BIT(RPMH_ACTIVE_ONLY_STATE)),	\
@@ -118,12 +121,19 @@ static DEFINE_MUTEX(rpmh_clk_lock); 
#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name,	\

			    _res_on, _div)				\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)

			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _div, false)



#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name,	\

				_div)					\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div)

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div, false)



#define DEFINE_CLK_RPMH_VRM_OPT(_platform, _name, _name_active,		\

			_res_name, _div)				\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div, true)







#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name)		\

	static struct clk_rpmh _platform##_##_name = {			\
@@ -368,17 +378,58 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 
	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),

};



DEFINE_CLK_RPMH_ARC(kona, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);

DEFINE_CLK_RPMH_VRM(kona, rf_clk1, rf_clk1_ao, "rfclka1", 1);

DEFINE_CLK_RPMH_VRM(kona, rf_clk3, rf_clk3_ao, "rfclka3", 1);

DEFINE_CLK_RPMH_VRM_OPT(kona, rf_clkd3, rf_clkd3_ao, "rfclkd3", 1);

DEFINE_CLK_RPMH_VRM_OPT(kona, rf_clkd4, rf_clkd4_ao, "rfclkd4", 1);



static struct clk_hw *kona_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &kona_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &kona_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK1]	= &kona_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]	= &kona_ln_bb_clk1_ao.hw,

	[RPMH_LN_BB_CLK2]	= &kona_ln_bb_clk2.hw,

	[RPMH_LN_BB_CLK2_A]	= &kona_ln_bb_clk2_ao.hw,

	[RPMH_LN_BB_CLK3]	= &kona_ln_bb_clk3.hw,

	[RPMH_LN_BB_CLK3_A]	= &kona_ln_bb_clk3_ao.hw,

	[RPMH_RF_CLK1]		= &kona_rf_clk1.hw,

	[RPMH_RF_CLK1_A]	= &kona_rf_clk1_ao.hw,

	[RPMH_RF_CLK3]		= &kona_rf_clk3.hw,

	[RPMH_RF_CLK3_A]	= &kona_rf_clk3_ao.hw,

	[RPMH_RF_CLKD3]		= &kona_rf_clkd3.hw,

	[RPMH_RF_CLKD3_A]	= &kona_rf_clkd3_ao.hw,

	[RPMH_RF_CLKD4]		= &kona_rf_clkd4.hw,

	[RPMH_RF_CLKD4_A]	= &kona_rf_clkd4_ao.hw,

};



static const struct clk_rpmh_desc clk_rpmh_kona = {

	.clks = kona_rpmh_clocks,

	.num_clks = ARRAY_SIZE(kona_rpmh_clocks),

};



static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,

					 void *data)

{

	struct clk_rpmh_desc *rpmh = data;

	unsigned int idx = clkspec->args[0];

	struct clk_rpmh *c;



	if (idx >= rpmh->num_clks) {

		pr_err("%s: invalid index %u\n", __func__, idx);

		return ERR_PTR(-EINVAL);

	}



	if (!rpmh->clks[idx])

		return ERR_PTR(-ENOENT);



	c = to_clk_rpmh(rpmh->clks[idx]);

	if (!c->res_addr)

		return ERR_PTR(-ENODEV);



	return rpmh->clks[idx];

}
@@ -400,9 +451,14 @@ static int clk_rpmh_probe(struct platform_device *pdev) 
		size_t aux_data_len;

		const struct bcm_db *data;



		if (!hw_clks[i])

			continue;



		rpmh_clk = to_clk_rpmh(hw_clks[i]);

		res_addr = cmd_db_read_addr(rpmh_clk->res_name);

		if (!res_addr) {

			if (rpmh_clk->optional)

				continue;

			dev_err(&pdev->dev, "missing RPMh resource address for %s\n",

				rpmh_clk->res_name);

			return -ENODEV;
@@ -447,6 +503,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) 


static const struct of_device_id clk_rpmh_match_table[] = {

	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},

	{ .compatible = "qcom,kona-rpmh-clk", .data = &clk_rpmh_kona},

	{ }

};

MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);

drivers/clk/qcom/clk-spmi-pmic-div.c

+4 −0
Original line number Diff line number Diff line
@@ -245,6 +245,10 @@ static int spmi_pmic_clkdiv_probe(struct platform_device *pdev) 
	}

	cxo_hz = clk_get_rate(cxo);

	clk_put(cxo);

	if (cxo_hz <= 0) {

		dev_err(dev, "invalid CXO rate: %d\n", cxo_hz);

		return -EINVAL;

	}



	parent_name = of_clk_get_parent_name(of_node, 0);

	if (!parent_name) {