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Commit 3a786966 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: power down/up uvd4 when smu disabled. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cbd9262f

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

+16 −1
Original line number Original line Diff line number Diff line
@@ -198,7 +198,6 @@ static int uvd_v4_2_hw_init(void *handle) 
	amdgpu_ring_commit(ring);

	amdgpu_ring_commit(ring);





done:

done:



	if (!r)

	if (!r)

		DRM_INFO("UVD initialized successfully.\n");

		DRM_INFO("UVD initialized successfully.\n");
@@ -694,8 +693,24 @@ static int uvd_v4_2_set_powergating_state(void *handle, 




	if (state == AMD_PG_STATE_GATE) {

	if (state == AMD_PG_STATE_GATE) {

		uvd_v4_2_stop(adev);

		uvd_v4_2_stop(adev);

		if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {

			if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) {

				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |

							UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |

							UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));

				mdelay(20);

			}

		}

		return 0;

		return 0;

	} else {

	} else {

		if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {

			if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) {

				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |

						UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |

						UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));

				mdelay(30);

			}

		}

		return uvd_v4_2_start(adev);

		return uvd_v4_2_start(adev);

	}

	}

}

}