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Commit 3a49d878 authored by Sudheer Papothi's avatar Sudheer Papothi Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update audio device tree overlay for lahaina 

Update audio device tree overlay with codec and speaker amplifier
configuration needed for lahaina target.

Change-Id: I4ffb9d20ead564e55b64f06050c620132cb688ac
parent 5b44375f

qcom/lahaina-audio-overlay.dtsi

+58 −116
Original line number Diff line number Diff line
@@ -42,18 +42,18 @@ 
			qcom,mipi-sdw-block-packing-mode = <1>;

			swrm-io-base = <0x3230000 0x0>;

			interrupts-extended =

				<&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 109 IRQ_TYPE_LEVEL_HIGH>;

				<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 130 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq", "swr_wake_irq";

			qcom,swr-wakeup-required = <1>;

			qcom,swr-num-ports = <5>;

			qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,

				<2 ADC1 0x1>, <2 ADC2 0x2>,

				<3 ADC3 0x1>, <3 ADC4 0x2>,

				<4 DMIC0 0x1>, <4 DMIC1 0x2>,

				<4 DMIC2 0x4>, <4 DMIC3 0x8>,

				<5 DMIC4 0x1>, <5 DMIC5 0x2>,

				<5 DMIC6 0x4>, <5 DMIC7 0x8>;

			qcom,swr-num-ports = <3>;

			qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,

				<1 SWRM_TX1_CH2 0x2>,

				<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,

				<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,

				<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,

				<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,

				<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			qcom,swr-mstr-irq-wakeup-capable = <1>;
@@ -72,7 +72,7 @@ 
			 <&clock_audio_rx_2 0>;

		qcom,rx-swr-gpios = <&rx_swr_gpios>;

		qcom,rx_mclk_mode_muxsel = <0x033240D8>;

		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;

		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;

		qcom,default-clk-id = <TX_CORE_CLK>;

		swr1: rx_swr_master {

			compatible = "qcom,swr-mstr";
@@ -85,14 +85,14 @@ 
			qcom,swr_master_id = <2>;

			qcom,mipi-sdw-block-packing-mode = <1>;

			swrm-io-base = <0x3210000 0x0>;

			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq";

			qcom,swr-num-ports = <5>;

			qcom,swr-num-ports = <6>;

			qcom,swr-port-mapping = <1 HPH_L 0x1>,

				<1 HPH_R 0x2>, <2 CLSH 0x1>,

				<3 COMP_L 0x1>, <3 COMP_R 0x2>,

				<4 LO 0x1>, <5 DSD_L 0x1>,

				<5 DSD_R 0x2>;

				<5 DSD_R 0x2>, <6 PCM_OUT1 0x0F>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			wcd938x_rx_slave: wcd938x-rx-slave {
@@ -109,7 +109,7 @@ 
		clocks = <&clock_audio_wsa_1 0>,

			 <&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;

		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;

		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;

		qcom,default-clk-id = <TX_CORE_CLK>;

		swr0: wsa_swr_master {

			compatible = "qcom,swr-mstr";
@@ -122,7 +122,7 @@ 
			qcom,swr_master_id = <1>;

			qcom,mipi-sdw-block-packing-mode = <0>;

			swrm-io-base = <0x3250000 0x0>;

			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq";

			qcom,swr-num-ports = <8>;

			qcom,swr-port-mapping = <1 SPKR_L 0x1>,
@@ -131,35 +131,30 @@ 
				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,

				<8 SPKR_R_VI 0x3>;

			qcom,swr-num-dev = <2>;

			wsa881x_0211: wsa881x@20170211 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x20170211>;

			wsa883x_0221: wsa883x@02170221 {

				compatible = "qcom,wsa883x";

				reg = <0x02 0x02170221>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;

				qcom,bolero-handle = <&bolero>;

			};



			wsa881x_0212: wsa881x@20170212 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x20170212>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;

			};



			wsa881x_0213: wsa881x@21170213 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x21170213>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;

				qcom,bolero-handle = <&bolero>;

				cdc-vdd-1p8-supply = <&S10B>;

				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;

				qcom,cdc-vdd-1p8-current = <20000>;

				qcom,cdc-static-supplies = "cdc-vdd-1p8";

			};



			wsa881x_0214: wsa881x@21170214 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x21170214>;

			wsa883x_0222: wsa883x@02170222 {

				compatible = "qcom,wsa883x";

				reg = <0x02 0x02170222>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;



				cdc-vdd-1p8-supply = <&S10B>;

				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;

				qcom,cdc-vdd-1p8-current = <20000>;

				qcom,cdc-static-supplies = "cdc-vdd-1p8";

			};

		};



	};



	wcd938x_codec: wcd938x-codec {
@@ -170,27 +165,35 @@ 
			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,

			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,

			<4 DSD_R 0x2 0 DSD_R>;

		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,

			<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,

			<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,

			<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,

			<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,

			<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,

			<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;



		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,

			<0 ADC2 0x2 0 SWRM_TX1_CH2>,

			<1 ADC3 0x1 0 SWRM_TX1_CH3>,

			<1 ADC4 0x2 0 SWRM_TX1_CH4>,

			<2 DMIC0 0x1 0 SWRM_TX2_CH1>,

			<2 DMIC1 0x2 0 SWRM_TX2_CH2>,

			<2 MBHC 0x4 0 SWRM_TX2_CH3>,

			<2 DMIC2 0x4 0 SWRM_TX2_CH3>,

			<2 DMIC3 0x8 0 SWRM_TX2_CH4>,

			<3 DMIC4 0x1 0 SWRM_TX3_CH1>,

			<3 DMIC5 0x2 0 SWRM_TX3_CH2>,

			<3 DMIC6 0x4 0 SWRM_TX3_CH3>,

			<3 DMIC7 0x8 0 SWRM_TX3_CH4>;

		qcom,dynamic-port-map-supported = <1>;



		qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;

		qcom,rx-slave = <&wcd938x_rx_slave>;

		qcom,tx-slave = <&wcd938x_tx_slave>;



		cdc-vdd-rxtx-supply = <&S4A>;

		cdc-vdd-rxtx-supply = <&S10B>;

		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;

		qcom,cdc-vdd-rxtx-current = <30000>;



		cdc-vddio-supply = <&S4A>;

		cdc-vddio-supply = <&S10B>;

		qcom,cdc-vddio-voltage = <1800000 1800000>;

		qcom,cdc-vddio-current = <30000>;



		cdc-vdd-buck-supply = <&S4A>;

		cdc-vdd-buck-supply = <&S10B>;

		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;

		qcom,cdc-vdd-buck-current = <650000>;
@@ -242,18 +245,6 @@ 
		"IN1_HPHL", "HPHL_OUT",

		"IN2_HPHR", "HPHR_OUT",

		"IN3_AUX", "AUX_OUT",

		"TX SWR_ADC0", "ADC1_OUTPUT",

		"TX SWR_ADC1", "ADC2_OUTPUT",

		"TX SWR_ADC2", "ADC3_OUTPUT",

		"TX SWR_ADC3", "ADC4_OUTPUT",

		"TX SWR_DMIC0", "DMIC1_OUTPUT",

		"TX SWR_DMIC1", "DMIC2_OUTPUT",

		"TX SWR_DMIC2", "DMIC3_OUTPUT",

		"TX SWR_DMIC3", "DMIC4_OUTPUT",

		"TX SWR_DMIC4", "DMIC5_OUTPUT",

		"TX SWR_DMIC5", "DMIC6_OUTPUT",

		"TX SWR_DMIC6", "DMIC7_OUTPUT",

		"TX SWR_DMIC7", "DMIC8_OUTPUT",

		"WSA SRC0_INP", "SRC0",

		"WSA_TX DEC0_INP", "TX DEC0 MUX",

		"WSA_TX DEC1_INP", "TX DEC1 MUX",
@@ -263,6 +254,9 @@ 
		"RX_TX DEC3_INP", "TX DEC3 MUX",

		"SpkrLeft IN", "WSA_SPK1 OUT",

		"SpkrRight IN", "WSA_SPK2 OUT",

		"TX SWR_INPUT", "WCD_TX_OUTPUT",

		"VA SWR_INPUT", "VA_TX_SWR_CLK",

		"VA SWR_INPUT", "WCD_TX_OUTPUT",

		"VA_AIF1 CAP", "VA_SWR_CLK",

		"VA_AIF2 CAP", "VA_SWR_CLK",

		"VA_AIF3 CAP", "VA_SWR_CLK",
@@ -277,36 +271,9 @@ 
		"VA DMIC2", "VA MIC BIAS1",

		"VA DMIC3", "VA MIC BIAS1",

		"VA DMIC4", "VA MIC BIAS4",

		"VA DMIC5", "VA MIC BIAS4",

		"VA SWR_ADC0", "VA_SWR_CLK",

		"VA SWR_ADC1", "VA_SWR_CLK",

		"VA SWR_ADC2", "VA_SWR_CLK",

		"VA SWR_ADC3", "VA_SWR_CLK",

		"VA SWR_MIC0", "VA_SWR_CLK",

		"VA SWR_MIC1", "VA_SWR_CLK",

		"VA SWR_MIC2", "VA_SWR_CLK",

		"VA SWR_MIC3", "VA_SWR_CLK",

		"VA SWR_MIC4", "VA_SWR_CLK",

		"VA SWR_MIC5", "VA_SWR_CLK",

		"VA SWR_MIC6", "VA_SWR_CLK",

		"VA SWR_MIC7", "VA_SWR_CLK",

		"VA SWR_ADC0", "ADC1_OUTPUT",

		"VA SWR_ADC1", "ADC2_OUTPUT",

		"VA SWR_ADC2", "ADC3_OUTPUT",

		"VA SWR_ADC3", "ADC4_OUTPUT",

		"VA SWR_MIC0", "DMIC1_OUTPUT",

		"VA SWR_MIC1", "DMIC2_OUTPUT",

		"VA SWR_MIC2", "DMIC3_OUTPUT",

		"VA SWR_MIC3", "DMIC4_OUTPUT",

		"VA SWR_MIC4", "DMIC5_OUTPUT",

		"VA SWR_MIC5", "DMIC6_OUTPUT",

		"VA SWR_MIC6", "DMIC7_OUTPUT",

		"VA SWR_MIC7", "DMIC8_OUTPUT";

		"VA DMIC5", "VA MIC BIAS4";

	qcom,msm-mbhc-hphl-swh = <1>;

	qcom,msm-mbhc-gnd-swh = <1>;

	qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;

	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;

	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;

	asoc-codec  = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;

	asoc-codec-names = "msm-stub-codec.1", "bolero_codec",

			   "msm-ext-disp-audio-codec-rx";
@@ -322,31 +289,6 @@ 
};



&q6core {

	cdc_dmic01_gpios: cdc_dmic01_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;

		pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;

		qcom,lpi-gpios;

	};



	cdc_dmic23_gpios: cdc_dmic23_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;

		pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;

		qcom,lpi-gpios;

	};



	cdc_dmic45_gpios: cdc_dmic45_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;

		pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;

		qcom,lpi-gpios;

		qcom,tlmm-gpio = <158>;

	};



	wsa_swr_gpios: wsa_swr_clk_data_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";
@@ -368,12 +310,12 @@ 
	tx_swr_gpios: tx_swr_clk_data_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active

			    &tx_swr_data2_active>;

		pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep

			    &tx_swr_data2_sleep>;

		pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active

			    &tx_swr_data1_active &tx_swr_data2_active>;

		pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep

			    &tx_swr_data1_sleep &tx_swr_data2_sleep>;

		qcom,lpi-gpios;

		qcom,tlmm-gpio = <147>;

		qcom,tlmm-gpio = <169>;

	};

};

qcom/lahaina-lpi.dtsi

+39 −9
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
		compatible = "qcom,lpi-pinctrl";

		reg = <0x33c0000 0x0>;

		qcom,slew-reg = <0x355a000 0x0>;

		qcom,num-gpios = <14>;

		qcom,num-gpios = <15>;

		gpio-controller;

		#gpio-cells = <2>;

		qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
@@ -12,14 +12,16 @@ 
				      <0x00006000>, <0x00007000>,

				      <0x00008000>, <0x00009000>,

				      <0x0000A000>, <0x0000B000>,

				      <0x0000C000>, <0x0000D000>;

				      <0x0000C000>, <0x0000D000>,

				      <0x0000E000>;

		qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,

					   <0x00000004>, <0x00000008>,

					   <0x0000000A>, <0x0000000C>,

					   <0x00000000>, <0x00000000>,

					   <0x00000000>, <0x00000000>,

					   <0x00000010>, <0x00000012>,

					   <0x00000000>, <0x00000000>;

					   <0x00000000>, <0x00000000>,

					   <0x00000006>;



		clock-names = "lpass_core_hw_vote";

		clocks = <&lpass_core_hw_vote 0>;
@@ -1372,7 +1374,7 @@ 
			};

		};



		tx_swr_data1_sleep: tx_swr_data1_sleep {

		tx_swr_data0_sleep: tx_swr_data0_sleep {

			mux {

				pins = "gpio1";

				function = "func1";
@@ -1386,7 +1388,7 @@ 
			};

		};



		tx_swr_data1_active: tx_swr_data1_active {

		tx_swr_data0_active: tx_swr_data0_active {

			mux {

				pins = "gpio1";

				function = "func1";
@@ -1400,7 +1402,7 @@ 
			};

		};



		tx_swr_data2_sleep: tx_swr_data2_sleep {

		tx_swr_data1_sleep: tx_swr_data1_sleep {

			mux {

				pins = "gpio2";

				function = "func1";
@@ -1414,7 +1416,7 @@ 
			};

		};



		tx_swr_data2_active: tx_swr_data2_active {

		tx_swr_data1_active: tx_swr_data1_active {

			mux {

				pins = "gpio2";

				function = "func1";
@@ -1428,6 +1430,34 @@ 
			};

		};



		tx_swr_data2_sleep: tx_swr_data2_sleep {

			mux {

				pins = "gpio14";

				function = "func1";

			};



			config {

				pins = "gpio14";

				drive-strength = <2>;

				input-enable;

				bias-pull-down;

			};

		};



		tx_swr_data2_active: tx_swr_data2_active {

			mux {

				pins = "gpio14";

				function = "func1";

			};



			config {

				pins = "gpio14";

				drive-strength = <2>;

				slew-rate = <1>;

				bias-bus-hold;

			};

		};



		rx_swr_clk_sleep: rx_swr_clk_sleep {

			mux {

				pins = "gpio3";
@@ -1487,7 +1517,7 @@ 
		rx_swr_data1_sleep: rx_swr_data1_sleep {

			mux {

				pins = "gpio5";

				function = "func2";

				function = "func1";

			};



			config {
@@ -1501,7 +1531,7 @@ 
		rx_swr_data1_active: rx_swr_data1_active {

			mux {

				pins = "gpio5";

				function = "func2";

				function = "func1";

			};



			config {

qcom/lahaina-pinctrl.dtsi

+89 −0
Original line number Diff line number Diff line
@@ -1384,6 +1384,95 @@ 
			};

		};



		/* WSA speaker reset pins */

		spkr_1_sd_n {

			spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {

				mux {

					pins = "gpio15";

					function = "gpio";

				};



				config {

					pins = "gpio15";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;

					input-enable;

				};

			};



			spkr_1_sd_n_active: spkr_1_sd_n_active {

				mux {

					pins = "gpio15";

					function = "gpio";

				};



				config {

					pins = "gpio15";

					drive-strength = <16>;   /* 16 mA */

					bias-disable;

					output-high;

				};

			};

		};



		spkr_2_sd_n {

			spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {

				mux {

					pins = "gpio42";

					function = "gpio";

				};



				config {

					pins = "gpio42";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;

					input-enable;

				};

			};



			spkr_2_sd_n_active: spkr_2_sd_n_active {

				mux {

					pins = "gpio42";

					function = "gpio";

				};



				config {

					pins = "gpio42";

					drive-strength = <16>;   /* 16 mA */

					bias-disable;

					output-high;

				};

			};

		};



		/* WCD reset pin */

		wcd938x_reset_active: wcd938x_reset_active {

			mux {

				pins = "gpio88";

				function = "gpio";

			};



			config {

				pins = "gpio88";

				drive-strength = <16>;

				output-high;

			};

		};



		wcd938x_reset_sleep: wcd938x_reset_sleep {

			mux {

				pins = "gpio88";

				function = "gpio";

			};



			config {

				pins = "gpio88";

				drive-strength = <16>;

				bias-disable;

				output-low;

			};

		};



		pcie0 {

			pcie0_perst_default: pcie0_perst_default {

				mux {