Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a031752 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.2-next-dts64' of... 

Merge tag 'v5.2-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

- convert arm boads to json-schema

mt8183:
- add base SoC and evaluation board
- add cpacity-dmips-mhz
- add pinctrl, auxadc, spi, and efuse nodes

* tag 'v5.2-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux

:
  arm64: dts: mt8183: add efuse and Mediatek Chip id node to read
  arm64: dts: mt8183: add spi node
  arm64: dts: mt8183: Add auxadc device node
  arm64: dts: mt8183: add pinctrl device node
  arm64: dts: mt8183: add capacity-dmips-mhz
  arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
  dt-bindings: arm: Convert MediaTek board/soc bindings to json-schema

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d78cda5a de103388

Documentation/devicetree/bindings/arm/mediatek.txt

deleted100644 → 0
+0 −89
Original line number Diff line number Diff line 
MediaTek SoC based Platforms Device Tree Bindings



Boards with a MediaTek SoC shall have the following property:



Required root node property:



compatible: Must contain one of

   "mediatek,mt2701"

   "mediatek,mt2712"

   "mediatek,mt6580"

   "mediatek,mt6589"

   "mediatek,mt6592"

   "mediatek,mt6755"

   "mediatek,mt6765"

   "mediatek,mt6795"

   "mediatek,mt6797"

   "mediatek,mt7622"

   "mediatek,mt7623"

   "mediatek,mt7629"

   "mediatek,mt8127"

   "mediatek,mt8135"

   "mediatek,mt8173"

   "mediatek,mt8183"





Supported boards:



- Evaluation board for MT2701:

    Required root node properties:

      - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";

- Evaluation board for MT2712:

    Required root node properties:

      - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";

- Evaluation board for MT6580:

    Required root node properties:

      - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";

- bq Aquaris5 smart phone:

    Required root node properties:

      - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";

- Evaluation board for MT6592:

    Required root node properties:

      - compatible = "mediatek,mt6592-evb", "mediatek,mt6592";

- Evaluation phone for MT6755(Helio P10):

    Required root node properties:

      - compatible = "mediatek,mt6755-evb", "mediatek,mt6755";

- Evaluation board for MT6765(Helio P22):

    Required root node properties:

      - compatible = "mediatek,mt6765-evb", "mediatek,mt6765";

- Evaluation board for MT6795(Helio X10):

    Required root node properties:

      - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";

- Evaluation board for MT6797(Helio X20):

    Required root node properties:

      - compatible = "mediatek,mt6797-evb", "mediatek,mt6797";

- Mediatek X20 Development Board:

    Required root node properties:

      - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";

- Reference board variant 1 for MT7622:

    Required root node properties:

      - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";

- Bananapi BPI-R64 for MT7622:

    Required root node properties:

      - compatible = "bananapi,bpi-r64", "mediatek,mt7622";

- Reference board for MT7623a with eMMC:

    Required root node properties:

      - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";

- Reference board for MT7623a with NAND:

    Required root node properties:

      - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";

- Reference board for MT7623n with eMMC:

    Required root node properties:

      - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";

- Bananapi BPI-R2 board:

      - compatible = "bananapi,bpi-r2", "mediatek,mt7623";

- Reference board for MT7629:

    Required root node properties:

      - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";

- MTK mt8127 tablet moose EVB:

    Required root node properties:

      - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";

- MTK mt8135 tablet EVB:

    Required root node properties:

      - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";

- MTK mt8173 tablet EVB:

    Required root node properties:

      - compatible = "mediatek,mt8173-evb", "mediatek,mt8173";

- Evaluation board for MT8183:

    Required root node properties:

      - compatible = "mediatek,mt8183-evb", "mediatek,mt8183";

Documentation/devicetree/bindings/arm/mediatek.yaml

0 → 100644
+91 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/mediatek.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek SoC based Platforms Device Tree Bindings



maintainers:

  - Sean Wang <sean.wang@mediatek.com>

  - Matthias Brugger <matthias.bgg@gmail.com>

description: |

  Boards with a MediaTek SoC shall have the following properties.



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - items:

          - enum:

              - mediatek,mt2701-evb

          - const: mediatek,mt2701



      - items:

          - enum:

              - mediatek,mt2712-evb

          - const: mediatek,mt2712

      - items:

          - enum:

              - mediatek,mt6580-evbp1

          - const: mediatek,mt6580

      - items:

          - enum:

              - mundoreader,bq-aquaris5

          - const: mediatek,mt6589

      - items:

          - enum:

              - mediatek,mt6592-evb

          - const: mediatek,mt6592

      - items:

          - enum:

              - mediatek,mt6755-evb

          - const: mediatek,mt6755

      - items:

          - enum:

              - mediatek,mt6765-evb

          - const: mediatek,mt6765

      - items:

          - enum:

              - mediatek,mt6795-evb

          - const: mediatek,mt6795

      - items:

          - enum:

              - archermind,mt6797-x20-dev

              - mediatek,mt6797-evb

          - const: mediatek,mt6797

      - items:

          - enum:

              - bananapi,bpi-r64

              - mediatek,mt7622-rfb1

          - const: mediatek,mt7622

      - items:

          - enum:

              - mediatek,mt7623a-rfb-emmc

              - mediatek,mt7623a-rfb-nand

              - mediatek,mt7623n-rfb-emmc

              - bananapi,bpi-r2

          - const: mediatek,mt7623



      - items:

          - enum:

              - mediatek,mt7629-rfb

          - const: mediatek,mt7629

      - items:

          - enum:

              - mediatek,mt8127-moose

          - const: mediatek,mt8127

      - items:

          - enum:

              - mediatek,mt8135-evbp1

          - const: mediatek,mt8135

      - items:

          - enum:

              - mediatek,mt8173-evb

          - const: mediatek,mt8173

      - items:

          - enum:

              - mediatek,mt8183-evb

          - const: mediatek,mt8183

...

arch/arm64/boot/dts/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb

arch/arm64/boot/dts/mediatek/mt8183-evb.dts

0 → 100644
+140 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (c) 2018 MediaTek Inc.

 * Author: Ben Ho <ben.ho@mediatek.com>

 *	   Erin Lo <erin.lo@mediatek.com>

 */



/dts-v1/;

#include "mt8183.dtsi"



/ {

	model = "MediaTek MT8183 evaluation board";

	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";



	aliases {

		serial0 = &uart0;

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x80000000>;

	};



	chosen {

		stdout-path = "serial0:921600n8";

	};

};



&auxadc {

	status = "okay";

};



&pio {

	spi_pins_0: spi0{

		pins_spi{

			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,

				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,

				 <PINMUX_GPIO87__FUNC_SPI0_MO>,

				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;

			bias-disable;

		};

	};



	spi_pins_1: spi1{

		pins_spi{

			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,

				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,

				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,

				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;

			bias-disable;

		};

	};



	spi_pins_2: spi2{

		pins_spi{

			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,

				 <PINMUX_GPIO1__FUNC_SPI2_MO>,

				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,

				 <PINMUX_GPIO94__FUNC_SPI2_MI>;

			bias-disable;

		};

	};



	spi_pins_3: spi3{

		pins_spi{

			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,

				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,

				 <PINMUX_GPIO23__FUNC_SPI3_MO>,

				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;

			bias-disable;

		};

	};



	spi_pins_4: spi4{

		pins_spi{

			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,

				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,

				 <PINMUX_GPIO19__FUNC_SPI4_MO>,

				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;

			bias-disable;

		};

	};



	spi_pins_5: spi5{

		pins_spi{

			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,

				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,

				 <PINMUX_GPIO15__FUNC_SPI5_MO>,

				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;

			bias-disable;

		};

	};

};



&spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_0>;

	mediatek,pad-select = <0>;

	status = "okay";

};



&spi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_1>;

	mediatek,pad-select = <0>;

	status = "okay";

};



&spi2 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_2>;

	mediatek,pad-select = <0>;

	status = "okay";

};



&spi3 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_3>;

	mediatek,pad-select = <0>;

	status = "okay";

};



&spi4 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_4>;

	mediatek,pad-select = <0>;

	status = "okay";

};



&spi5 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_5>;

	mediatek,pad-select = <0>;

	status = "okay";



};



&uart0 {

	status = "okay";

};

arch/arm64/boot/dts/mediatek/mt8183.dtsi

0 → 100644
+447 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (c) 2018 MediaTek Inc.

 * Author: Ben Ho <ben.ho@mediatek.com>

 *	   Erin Lo <erin.lo@mediatek.com>

 */



#include <dt-bindings/clock/mt8183-clk.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include "mt8183-pinfunc.h"



/ {

	compatible = "mediatek,mt8183";

	interrupt-parent = <&sysirq>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0>;

				};

				core1 {

					cpu = <&cpu1>;

				};

				core2 {

					cpu = <&cpu2>;

				};

				core3 {

					cpu = <&cpu3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu4>;

				};

				core1 {

					cpu = <&cpu5>;

				};

				core2 {

					cpu = <&cpu6>;

				};

				core3 {

					cpu = <&cpu7>;

				};

			};

		};



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x000>;

			enable-method = "psci";

			capacity-dmips-mhz = <741>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x001>;

			enable-method = "psci";

			capacity-dmips-mhz = <741>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x002>;

			enable-method = "psci";

			capacity-dmips-mhz = <741>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x003>;

			enable-method = "psci";

			capacity-dmips-mhz = <741>;

		};



		cpu4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

		};



		cpu5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x101>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

		};



		cpu6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x102>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

		};



		cpu7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x103>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

		};

	};



	pmu-a53 {

		compatible = "arm,cortex-a53-pmu";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;

	};



	pmu-a73 {

		compatible = "arm,cortex-a73-pmu";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;

	};



	psci {

		compatible      = "arm,psci-1.0";

		method          = "smc";

	};



	clk26m: oscillator {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <26000000>;

		clock-output-names = "clk26m";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;

	};



	soc {

		#address-cells = <2>;

		#size-cells = <2>;

		compatible = "simple-bus";

		ranges;



		soc_data: soc_data@8000000 {

			compatible = "mediatek,mt8183-efuse",

				     "mediatek,efuse";

			reg = <0 0x08000000 0 0x0010>;

			#address-cells = <1>;

			#size-cells = <1>;

			status = "disabled";

		};



		gic: interrupt-controller@c000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <4>;

			interrupt-parent = <&gic>;

			interrupt-controller;

			reg = <0 0x0c000000 0 0x40000>,  /* GICD */

			      <0 0x0c100000 0 0x200000>, /* GICR */

			      <0 0x0c400000 0 0x2000>,   /* GICC */

			      <0 0x0c410000 0 0x1000>,   /* GICH */

			      <0 0x0c420000 0 0x2000>;   /* GICV */



			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;

			ppi-partitions {

				ppi_cluster0: interrupt-partition-0 {

					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;

				};

				ppi_cluster1: interrupt-partition-1 {

					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;

				};

			};

		};



		mcucfg: syscon@c530000 {

			compatible = "mediatek,mt8183-mcucfg", "syscon";

			reg = <0 0x0c530000 0 0x1000>;

			#clock-cells = <1>;

		};



		sysirq: interrupt-controller@c530a80 {

			compatible = "mediatek,mt8183-sysirq",

				     "mediatek,mt6577-sysirq";

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupt-parent = <&gic>;

			reg = <0 0x0c530a80 0 0x50>;

		};



		topckgen: syscon@10000000 {

			compatible = "mediatek,mt8183-topckgen", "syscon";

			reg = <0 0x10000000 0 0x1000>;

			#clock-cells = <1>;

		};



		infracfg: syscon@10001000 {

			compatible = "mediatek,mt8183-infracfg", "syscon";

			reg = <0 0x10001000 0 0x1000>;

			#clock-cells = <1>;

		};



		pio: pinctrl@10005000 {

			compatible = "mediatek,mt8183-pinctrl";

			reg = <0 0x10005000 0 0x1000>,

			      <0 0x11f20000 0 0x1000>,

			      <0 0x11e80000 0 0x1000>,

			      <0 0x11e70000 0 0x1000>,

			      <0 0x11e90000 0 0x1000>,

			      <0 0x11d30000 0 0x1000>,

			      <0 0x11d20000 0 0x1000>,

			      <0 0x11c50000 0 0x1000>,

			      <0 0x11f30000 0 0x1000>,

			      <0 0x1000b000 0 0x1000>;

			reg-names = "iocfg0", "iocfg1", "iocfg2",

				    "iocfg3", "iocfg4", "iocfg5",

				    "iocfg6", "iocfg7", "iocfg8",

				    "eint";

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pio 0 0 192>;

			interrupt-controller;

			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <2>;

		};



		apmixedsys: syscon@1000c000 {

			compatible = "mediatek,mt8183-apmixedsys", "syscon";

			reg = <0 0x1000c000 0 0x1000>;

			#clock-cells = <1>;

		};



		pwrap: pwrap@1000d000 {

			compatible = "mediatek,mt8183-pwrap";

			reg = <0 0x1000d000 0 0x1000>;

			reg-names = "pwrap";

			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,

				 <&infracfg CLK_INFRA_PMIC_AP>;

			clock-names = "spi", "wrap";

		};



		auxadc: auxadc@11001000 {

			compatible = "mediatek,mt8183-auxadc",

				     "mediatek,mt8173-auxadc";

			reg = <0 0x11001000 0 0x1000>;

			clocks = <&infracfg CLK_INFRA_AUXADC>;

			clock-names = "main";

			#io-channel-cells = <1>;

			status = "disabled";

		};



		uart0: serial@11002000 {

			compatible = "mediatek,mt8183-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x1000>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;

			clock-names = "baud", "bus";

			status = "disabled";

		};



		uart1: serial@11003000 {

			compatible = "mediatek,mt8183-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x1000>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;

			clock-names = "baud", "bus";

			status = "disabled";

		};



		uart2: serial@11004000 {

			compatible = "mediatek,mt8183-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x1000>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;

			clock-names = "baud", "bus";

			status = "disabled";

		};



		spi0: spi@1100a000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x1100a000 0 0x1000>;

			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI0>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		spi1: spi@11010000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x11010000 0 0x1000>;

			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI1>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		spi2: spi@11012000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x11012000 0 0x1000>;

			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI2>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		spi3: spi@11013000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x11013000 0 0x1000>;

			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI3>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		spi4: spi@11018000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x11018000 0 0x1000>;

			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI4>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		spi5: spi@11019000 {

			compatible = "mediatek,mt8183-spi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0x11019000 0 0x1000>;

			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,

				 <&topckgen CLK_TOP_MUX_SPI>,

				 <&infracfg CLK_INFRA_SPI5>;

			clock-names = "parent-clk", "sel-clk", "spi-clk";

			status = "disabled";

		};



		audiosys: syscon@11220000 {

			compatible = "mediatek,mt8183-audiosys", "syscon";

			reg = <0 0x11220000 0 0x1000>;

			#clock-cells = <1>;

		};



		efuse: efuse@11f10000 {

			compatible = "mediatek,mt8183-efuse",

				     "mediatek,efuse";

			reg = <0 0x11f10000 0 0x1000>;

		};



		mfgcfg: syscon@13000000 {

			compatible = "mediatek,mt8183-mfgcfg", "syscon";

			reg = <0 0x13000000 0 0x1000>;

			#clock-cells = <1>;

		};



		mmsys: syscon@14000000 {

			compatible = "mediatek,mt8183-mmsys", "syscon";

			reg = <0 0x14000000 0 0x1000>;

			#clock-cells = <1>;

		};



		imgsys: syscon@15020000 {

			compatible = "mediatek,mt8183-imgsys", "syscon";

			reg = <0 0x15020000 0 0x1000>;

			#clock-cells = <1>;

		};



		vdecsys: syscon@16000000 {

			compatible = "mediatek,mt8183-vdecsys", "syscon";

			reg = <0 0x16000000 0 0x1000>;

			#clock-cells = <1>;

		};



		vencsys: syscon@17000000 {

			compatible = "mediatek,mt8183-vencsys", "syscon";

			reg = <0 0x17000000 0 0x1000>;

			#clock-cells = <1>;

		};



		ipu_conn: syscon@19000000 {

			compatible = "mediatek,mt8183-ipu_conn", "syscon";

			reg = <0 0x19000000 0 0x1000>;

			#clock-cells = <1>;

		};



		ipu_adl: syscon@19010000 {

			compatible = "mediatek,mt8183-ipu_adl", "syscon";

			reg = <0 0x19010000 0 0x1000>;

			#clock-cells = <1>;

		};



		ipu_core0: syscon@19180000 {

			compatible = "mediatek,mt8183-ipu_core0", "syscon";

			reg = <0 0x19180000 0 0x1000>;

			#clock-cells = <1>;

		};



		ipu_core1: syscon@19280000 {

			compatible = "mediatek,mt8183-ipu_core1", "syscon";

			reg = <0 0x19280000 0 0x1000>;

			#clock-cells = <1>;

		};



		camsys: syscon@1a000000 {

			compatible = "mediatek,mt8183-camsys", "syscon";

			reg = <0 0x1a000000 0 0x1000>;

			#clock-cells = <1>;

		};

	};

};