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Commit 39defc81 authored by Andre Przywara's avatar Andre Przywara Committed by Chen-Yu Tsai
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arm64: dts: allwinner: a64: Add L2 cache nodes 



Current kernels complain when booting on an A64 Soc:
....
[    1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.

Add the L2 cache node and let each CPU point to it.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent fcddd1f6

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
			device_type = "cpu";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&L2>;

		};



		cpu1: cpu@1 {
@@ -95,6 +96,7 @@ 
			device_type = "cpu";

			reg = <1>;

			enable-method = "psci";

			next-level-cache = <&L2>;

		};



		cpu2: cpu@2 {
@@ -102,6 +104,7 @@ 
			device_type = "cpu";

			reg = <2>;

			enable-method = "psci";

			next-level-cache = <&L2>;

		};



		cpu3: cpu@3 {
@@ -109,6 +112,12 @@ 
			device_type = "cpu";

			reg = <3>;

			enable-method = "psci";

			next-level-cache = <&L2>;

		};



		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};