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Commit 39bf9985 authored by Julien Masson's avatar Julien Masson Committed by Neil Armstrong
Browse files

drm: meson: crtc: use proper macros instead of magic constants 



This patch add new macros which describe couple bits field of the
following registers:
- VD1_BLEND_SRC_CTRL
- VPP_SC_MISC

Signed-off-by: default avatarJulien Masson <jmasson@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86wohb82fa.fsf@baylibre.com
parent f237bf2d

drivers/gpu/drm/meson/meson_crtc.c

+11 −6
Original line number Diff line number Diff line
@@ -265,10 +265,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv) 


static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)

{

	writel_relaxed(((1 << 16) | /* post bld premult*/

			(1 << 8) | /* post src */

			(1 << 4) | /* pre bld premult*/

			(1 << 0)),

	writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 |

		       VD_BLEND_PREBLD_PREMULT_EN |

		       VD_BLEND_POSTBLD_SRC_VD1 |

		       VD_BLEND_POSTBLD_PREMULT_EN,

		       priv->io_base + _REG(VD1_BLEND_SRC_CTRL));

}
@@ -487,7 +487,12 @@ void meson_crtc_irq(struct meson_drm *priv) 
		writel_relaxed(priv->viu.vd1_range_map_cr,

				priv->io_base + meson_crtc->viu_offset +

				_REG(VD1_IF0_RANGE_MAP_CR));

		writel_relaxed(0x78404,

		writel_relaxed(VPP_VSC_BANK_LENGTH(4) |

			       VPP_HSC_BANK_LENGTH(4) |

			       VPP_SC_VD_EN_ENABLE |

			       VPP_SC_TOP_EN_ENABLE |

			       VPP_SC_HSC_EN_ENABLE |

			       VPP_SC_VSC_EN_ENABLE,

				priv->io_base + _REG(VPP_SC_MISC));

		writel_relaxed(priv->viu.vpp_pic_in_height,

				priv->io_base + _REG(VPP_PIC_IN_HEIGHT));

drivers/gpu/drm/meson/meson_registers.h

+16 −0
Original line number Diff line number Diff line
@@ -362,6 +362,12 @@ 
#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17

#define VPP_HSC_PHASE_CTRL 0x1d18

#define VPP_SC_MISC 0x1d19

#define		VPP_SC_VD_EN_ENABLE             BIT(15)

#define		VPP_SC_TOP_EN_ENABLE            BIT(16)

#define		VPP_SC_HSC_EN_ENABLE            BIT(17)

#define		VPP_SC_VSC_EN_ENABLE            BIT(18)

#define		VPP_VSC_BANK_LENGTH(length)     (length & 0x7)

#define		VPP_HSC_BANK_LENGTH(length)     ((length & 0x7) << 8)

#define VPP_PREBLEND_VD1_H_START_END 0x1d1a

#define VPP_PREBLEND_VD1_V_START_END 0x1d1b

#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
@@ -1630,6 +1636,16 @@ 
#define VPP_SLEEP_CTRL 0x1dfa

#define VD1_BLEND_SRC_CTRL 0x1dfb

#define VD2_BLEND_SRC_CTRL 0x1dfc

#define		VD_BLEND_PREBLD_SRC_VD1         (1 << 0)

#define		VD_BLEND_PREBLD_SRC_VD2         (2 << 0)

#define		VD_BLEND_PREBLD_SRC_OSD1        (3 << 0)

#define		VD_BLEND_PREBLD_SRC_OSD2        (4 << 0)

#define		VD_BLEND_PREBLD_PREMULT_EN      BIT(4)

#define		VD_BLEND_POSTBLD_SRC_VD1        (1 << 8)

#define		VD_BLEND_POSTBLD_SRC_VD2        (2 << 8)

#define		VD_BLEND_POSTBLD_SRC_OSD1       (3 << 8)

#define		VD_BLEND_POSTBLD_SRC_OSD2       (4 << 8)

#define		VD_BLEND_POSTBLD_PREMULT_EN     BIT(16)

#define OSD1_BLEND_SRC_CTRL 0x1dfd

#define OSD2_BLEND_SRC_CTRL 0x1dfe