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Commit 3975797f authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued 



Tvrtko needs

commit b3c11ac2
Author: Eric Engestrom <eric@engestrom.ch>
Date:   Sat Nov 12 01:12:56 2016 +0000

    drm: move allocation out of drm_get_format_name()

to be able to apply his patches without conflicts.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parents 78424c92 b7c0e47d

CREDITS

+3 −2
Original line number Diff line number Diff line
@@ -1864,10 +1864,11 @@ S: The Netherlands 


N: Martin Kepplinger

E: martink@posteo.de

E: martin.kepplinger@theobroma-systems.com

E: martin.kepplinger@ginzinger.com

W: http://www.martinkepplinger.com

D: mma8452 accelerators iio driver

D: Kernel cleanups

D: pegasus_notetaker input driver

D: Kernel fixes and cleanups

S: Garnisonstraße 26

S: 4020 Linz

S: Austria

Documentation/device-mapper/dm-raid.txt

+1 −0
Original line number Diff line number Diff line
@@ -309,3 +309,4 @@ Version History 
	with a reshape in progress.

1.9.0   Add support for RAID level takeover/reshape/region size

	and set size reduction.

1.9.1   Fix activation of existing RAID 4/10 mapped devices

Documentation/devicetree/bindings/clock/uniphier-clock.txt

+8 −8
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ Example: 
		reg = <0x61840000 0x4000>;



		clock {

			compatible = "socionext,uniphier-ld20-clock";

			compatible = "socionext,uniphier-ld11-clock";

			#clock-cells = <1>;

		};
@@ -43,8 +43,8 @@ Provided clocks: 
21: USB3 ch1 PHY1





Media I/O (MIO) clock

---------------------

Media I/O (MIO) clock, SD clock

-------------------------------



Required properties:

- compatible: should be one of the following:
@@ -52,10 +52,10 @@ Required properties: 
    "socionext,uniphier-ld4-mio-clock"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.

    "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.

    "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.

    "socionext,uniphier-pro5-sd-clock"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-sd-clock"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.

    "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.

    "socionext,uniphier-ld20-sd-clock"  - for LD20 SoC.

- #clock-cells: should be 1.



Example:
@@ -66,7 +66,7 @@ Example: 
		reg = <0x59810000 0x800>;



		clock {

			compatible = "socionext,uniphier-ld20-mio-clock";

			compatible = "socionext,uniphier-ld11-mio-clock";

			#clock-cells = <1>;

		};
@@ -112,7 +112,7 @@ Example: 
		reg = <0x59820000 0x200>;



		clock {

			compatible = "socionext,uniphier-ld20-peri-clock";

			compatible = "socionext,uniphier-ld11-peri-clock";

			#clock-cells = <1>;

		};

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt

+3 −1
Original line number Diff line number Diff line
@@ -19,7 +19,9 @@ Required properties: 


Optional properties

- reg-io-width: the width of the reg:1,4, default set to 1 if not present

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,

  if the property is omitted, a functionally reduced I2C bus

  controller on DW HDMI is probed

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



Example:

Documentation/devicetree/bindings/display/panel/display-timing.txt

+8 −0
Original line number Diff line number Diff line
@@ -32,6 +32,14 @@ optional properties: 
			- active low  = drive pixel data on falling edge/

					sample data on rising edge

			- ignored     = ignored

 - syncclk-active: with

			- active high = drive sync on rising edge/

					sample sync on falling edge of pixel

					clock

			- active low  = drive sync on falling edge/

					sample sync on rising edge of pixel

					clock

			- omitted     = same configuration as pixelclk-active

 - interlaced (bool): boolean to enable interlaced mode

 - doublescan (bool): boolean to enable doublescan mode

 - doubleclk (bool): boolean to enable doubleclock mode