Loading asoc/codecs/bolero/bolero-cdc.c +12 −0 Original line number Diff line number Diff line Loading @@ -836,6 +836,18 @@ static int bolero_ssr_enable(struct device *dev, void *data) BOLERO_MACRO_EVT_CLK_RESET, 0x0); } trace_printk("%s: clk count reset\n", __func__); if (priv->rsc_clk_cb) priv->rsc_clk_cb(priv->clk_dev, BOLERO_MACRO_EVT_SSR_GFMUX_UP); for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) { if (!priv->macro_params[macro_idx].event_handler) continue; priv->macro_params[macro_idx].event_handler( priv->component, BOLERO_MACRO_EVT_PRE_SSR_UP, 0x0); } regcache_cache_only(priv->regmap, false); mutex_lock(&priv->clk_lock); priv->dev_up = true; Loading asoc/codecs/bolero/bolero-cdc.h +3 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,9 @@ enum { BOLERO_MACRO_EVT_CLK_RESET, BOLERO_MACRO_EVT_REG_WAKE_IRQ, BOLERO_MACRO_EVT_RX_COMPANDER_SOFT_RST, BOLERO_MACRO_EVT_BCS_CLK_OFF BOLERO_MACRO_EVT_BCS_CLK_OFF, BOLERO_MACRO_EVT_SSR_GFMUX_UP, BOLERO_MACRO_EVT_PRE_SSR_UP, }; enum { Loading asoc/codecs/bolero/bolero-clk-rsc.c +20 −10 Original line number Diff line number Diff line Loading @@ -38,6 +38,7 @@ struct bolero_clk_rsc { int reg_seq_en_cnt; int va_tx_clk_cnt; bool dev_up; bool dev_up_gfmux; u32 num_fs_reg; u32 *fs_gen_seq; int default_clk_id[MAX_CLK]; Loading Loading @@ -65,10 +66,14 @@ static int bolero_clk_rsc_cb(struct device *dev, u16 event) } mutex_lock(&priv->rsc_clk_lock); if (event == BOLERO_MACRO_EVT_SSR_UP) if (event == BOLERO_MACRO_EVT_SSR_UP) { priv->dev_up = true; else if (event == BOLERO_MACRO_EVT_SSR_DOWN) } else if (event == BOLERO_MACRO_EVT_SSR_DOWN) { priv->dev_up = false; priv->dev_up_gfmux = false; } else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) { priv->dev_up_gfmux = true; } mutex_unlock(&priv->rsc_clk_lock); return 0; Loading Loading @@ -282,10 +287,12 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * care in DSP itself */ if (clk_id != VA_CORE_CLK) { if (priv->dev_up_gfmux) { iowrite32(0x1, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after enable: %d\n", __func__, muxsel); } bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false); Loading Loading @@ -313,12 +320,14 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * This configuration would be taken * care in DSP itself. */ if (priv->dev_up_gfmux) { iowrite32(0x0, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after disable: %d\n", __func__, muxsel); } } } if (priv->clk[clk_id + NPL_CLK_OFFSET]) clk_disable_unprepare( priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -706,6 +715,7 @@ static int bolero_clk_rsc_probe(struct platform_device *pdev) } priv->dev = &pdev->dev; priv->dev_up = true; priv->dev_up_gfmux = true; mutex_init(&priv->rsc_clk_lock); mutex_init(&priv->fs_gen_lock); dev_set_drvdata(&pdev->dev, priv); Loading asoc/codecs/bolero/rx-macro.c +7 −5 Original line number Diff line number Diff line Loading @@ -1410,11 +1410,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, } } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; case BOLERO_MACRO_EVT_PRE_SSR_UP: /* enable&disable RX_CORE_CLK to reset GFMUX reg */ ret = bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, Loading @@ -1427,6 +1423,12 @@ static int rx_macro_event_handler(struct snd_soc_component *component, bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, RX_CORE_CLK, false); break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; if (rx_priv->swr_ctrl_data) swrm_wcd_notify( Loading asoc/codecs/bolero/tx-macro.c +3 −0 Original line number Diff line number Diff line Loading @@ -411,6 +411,9 @@ static int tx_macro_event_handler(struct snd_soc_component *component, else tx_priv->hs_slow_insert_complete = false; break; default: pr_debug("%s Invalid Event\n", __func__); break; } return 0; } Loading Loading
asoc/codecs/bolero/bolero-cdc.c +12 −0 Original line number Diff line number Diff line Loading @@ -836,6 +836,18 @@ static int bolero_ssr_enable(struct device *dev, void *data) BOLERO_MACRO_EVT_CLK_RESET, 0x0); } trace_printk("%s: clk count reset\n", __func__); if (priv->rsc_clk_cb) priv->rsc_clk_cb(priv->clk_dev, BOLERO_MACRO_EVT_SSR_GFMUX_UP); for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) { if (!priv->macro_params[macro_idx].event_handler) continue; priv->macro_params[macro_idx].event_handler( priv->component, BOLERO_MACRO_EVT_PRE_SSR_UP, 0x0); } regcache_cache_only(priv->regmap, false); mutex_lock(&priv->clk_lock); priv->dev_up = true; Loading
asoc/codecs/bolero/bolero-cdc.h +3 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,9 @@ enum { BOLERO_MACRO_EVT_CLK_RESET, BOLERO_MACRO_EVT_REG_WAKE_IRQ, BOLERO_MACRO_EVT_RX_COMPANDER_SOFT_RST, BOLERO_MACRO_EVT_BCS_CLK_OFF BOLERO_MACRO_EVT_BCS_CLK_OFF, BOLERO_MACRO_EVT_SSR_GFMUX_UP, BOLERO_MACRO_EVT_PRE_SSR_UP, }; enum { Loading
asoc/codecs/bolero/bolero-clk-rsc.c +20 −10 Original line number Diff line number Diff line Loading @@ -38,6 +38,7 @@ struct bolero_clk_rsc { int reg_seq_en_cnt; int va_tx_clk_cnt; bool dev_up; bool dev_up_gfmux; u32 num_fs_reg; u32 *fs_gen_seq; int default_clk_id[MAX_CLK]; Loading Loading @@ -65,10 +66,14 @@ static int bolero_clk_rsc_cb(struct device *dev, u16 event) } mutex_lock(&priv->rsc_clk_lock); if (event == BOLERO_MACRO_EVT_SSR_UP) if (event == BOLERO_MACRO_EVT_SSR_UP) { priv->dev_up = true; else if (event == BOLERO_MACRO_EVT_SSR_DOWN) } else if (event == BOLERO_MACRO_EVT_SSR_DOWN) { priv->dev_up = false; priv->dev_up_gfmux = false; } else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) { priv->dev_up_gfmux = true; } mutex_unlock(&priv->rsc_clk_lock); return 0; Loading Loading @@ -282,10 +287,12 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * care in DSP itself */ if (clk_id != VA_CORE_CLK) { if (priv->dev_up_gfmux) { iowrite32(0x1, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after enable: %d\n", __func__, muxsel); } bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false); Loading Loading @@ -313,12 +320,14 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * This configuration would be taken * care in DSP itself. */ if (priv->dev_up_gfmux) { iowrite32(0x0, clk_muxsel); muxsel = ioread32(clk_muxsel); trace_printk("%s: muxsel value after disable: %d\n", __func__, muxsel); } } } if (priv->clk[clk_id + NPL_CLK_OFFSET]) clk_disable_unprepare( priv->clk[clk_id + NPL_CLK_OFFSET]); Loading Loading @@ -706,6 +715,7 @@ static int bolero_clk_rsc_probe(struct platform_device *pdev) } priv->dev = &pdev->dev; priv->dev_up = true; priv->dev_up_gfmux = true; mutex_init(&priv->rsc_clk_lock); mutex_init(&priv->fs_gen_lock); dev_set_drvdata(&pdev->dev, priv); Loading
asoc/codecs/bolero/rx-macro.c +7 −5 Original line number Diff line number Diff line Loading @@ -1410,11 +1410,7 @@ static int rx_macro_event_handler(struct snd_soc_component *component, } } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; case BOLERO_MACRO_EVT_PRE_SSR_UP: /* enable&disable RX_CORE_CLK to reset GFMUX reg */ ret = bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, Loading @@ -1427,6 +1423,12 @@ static int rx_macro_event_handler(struct snd_soc_component *component, bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, RX_CORE_CLK, false); break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); rx_priv->dev_up = true; /* reset swr after ssr/pdr */ rx_priv->reset_swr = true; if (rx_priv->swr_ctrl_data) swrm_wcd_notify( Loading
asoc/codecs/bolero/tx-macro.c +3 −0 Original line number Diff line number Diff line Loading @@ -411,6 +411,9 @@ static int tx_macro_event_handler(struct snd_soc_component *component, else tx_priv->hs_slow_insert_complete = false; break; default: pr_debug("%s Invalid Event\n", __func__); break; } return 0; } Loading