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Commit 38fd94b0 authored by Christopher Covington's avatar Christopher Covington Committed by Will Deacon
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arm64: Work around Falkor erratum 1003 



The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
is triggered, page table entries using the new translation table base
address (BADDR) will be allocated into the TLB using the old ASID. All
circumstances leading to the incorrect ASID being cached in the TLB arise
when software writes TTBRx_EL1[ASID] and TTBRx_EL1[BADDR], a memory
operation is in the process of performing a translation using the specific
TTBRx_EL1 being written, and the memory operation uses a translation table
descriptor designated as non-global. EL2 and EL3 code changing the EL1&0
ASID is not subject to this erratum because hardware is prohibited from
performing translations from an out-of-context translation regime.

Consider the following pseudo code.

  write new BADDR and ASID values to TTBRx_EL1

Replacing the above sequence with the one below will ensure that no TLB
entries with an incorrect ASID are used by software.

  write reserved value to TTBRx_EL1[ASID]
  ISB
  write new value to TTBRx_EL1[BADDR]
  ISB
  write new value to TTBRx_EL1[ASID]
  ISB

When the above sequence is used, page table entries using the new BADDR
value may still be incorrectly allocated into the TLB using the reserved
ASID. Yet this will not reduce functionality, since TLB entries incorrectly
tagged with the reserved ASID will never be hit by a later instruction.

Based on work by Shanker Donthineni <shankerd@codeaurora.org>

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarChristopher Covington <cov@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 2bf47e19

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -66,4 +66,5 @@ stable kernels. 
|                |                 |                 |                             |

| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |

|                |                 |                 |                             |

| Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

arch/arm64/Kconfig

+18 −0
Original line number Diff line number Diff line
@@ -480,6 +480,24 @@ config CAVIUM_ERRATUM_27456 


	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

	select ARM64_PAN if ARM64_SW_TTBR0_PAN

	help

	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID

	  and BADDR are changed together in TTBRx_EL1. The workaround for this

	  issue is to use a reserved ASID in cpu_do_switch_mm() before

	  switching to the new ASID. Saying Y here selects ARM64_PAN if

	  ARM64_SW_TTBR0_PAN is selected. This is done because implementing and

	  maintaining the E1003 workaround in the software PAN emulation code

	  would be an unnecessary complication. The affected Falkor v1 CPU

	  implements ARMv8.1 hardware PAN support and using hardware PAN

	  support versus software PAN emulation is mutually exclusive at

	  runtime.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1009

	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"

	default y

arch/arm64/include/asm/assembler.h

+23 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/mmu_context.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>
@@ -422,6 +423,28 @@ alternative_endif 
	mrs	\rd, sp_el0

	.endm



/*

 * Errata workaround prior to TTBR0_EL1 update

 *

 * 	val:	TTBR value with new BADDR, preserved

 * 	tmp0:	temporary register, clobbered

 * 	tmp1:	other temporary register, clobbered

 */

	.macro	pre_ttbr0_update_workaround, val, tmp0, tmp1

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003

	mrs	\tmp0, ttbr0_el1

	mov	\tmp1, #FALKOR_RESERVED_ASID

	bfi	\tmp0, \tmp1, #48, #16		// reserved ASID + old BADDR

	msr	ttbr0_el1, \tmp0

	isb

	bfi	\tmp0, \val, #0, #48		// reserved ASID + new BADDR

	msr	ttbr0_el1, \tmp0

	isb

alternative_else_nop_endif

#endif

	.endm



/*

 * Errata workaround post TTBR0_EL1 update.

 */

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ 
#define ARM64_MISMATCHED_CACHE_LINE_SIZE	15

#define ARM64_HAS_NO_FPSIMD			16

#define ARM64_WORKAROUND_REPEAT_TLBI		17

#define ARM64_WORKAROUND_QCOM_FALKOR_E1003	18



#define ARM64_NCAPS				18

#define ARM64_NCAPS				19



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/mmu_context.h

+7 −1
Original line number Diff line number Diff line
@@ -19,6 +19,10 @@ 
#ifndef __ASM_MMU_CONTEXT_H

#define __ASM_MMU_CONTEXT_H



#define FALKOR_RESERVED_ASID	1



#ifndef __ASSEMBLY__



#include <linux/compiler.h>

#include <linux/sched.h>
@@ -220,4 +224,6 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, 


void verify_cpu_asid_bits(void);



#endif
 
#endif /* !__ASSEMBLY__ */



#endif /* !__ASM_MMU_CONTEXT_H */