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Commit 38df0701 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: reset drr programming on pipe reset 



[why]
drr is still enabled after driver is unloaded causing black screen

[how]
disable drr during pipe reset.

Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d19c73f

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −0
Original line number Diff line number Diff line
@@ -823,6 +823,9 @@ static void dcn10_reset_back_end_for_pipe( 
		pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);



		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

		if (pipe_ctx->stream_res.tg->funcs->set_drr)

			pipe_ctx->stream_res.tg->funcs->set_drr(

					pipe_ctx->stream_res.tg, NULL);

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+4 −0
Original line number Diff line number Diff line
@@ -1834,6 +1834,10 @@ static void dcn20_reset_back_end_for_pipe( 
		if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

			pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);



		if (pipe_ctx->stream_res.tg->funcs->set_drr)

			pipe_ctx->stream_res.tg->funcs->set_drr(

					pipe_ctx->stream_res.tg, NULL);

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++)