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Commit 38ddf41b authored by Joerg Roedel's avatar Joerg Roedel Committed by Ingo Molnar
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AMD IOMMU: some set_device_domain cleanups 



Remove some magic numbers and split the pte_root using standard
functions.

Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent bd60b735

arch/x86/kernel/amd_iommu.c

+5 −4
Original line number Original line Diff line number Diff line
@@ -739,12 +739,13 @@ static void set_device_domain(struct amd_iommu *iommu, 




	u64 pte_root = virt_to_phys(domain->pt_root);

	u64 pte_root = virt_to_phys(domain->pt_root);





	pte_root |= (domain->mode & 0x07) << 9;

	pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)

	pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;

		    << DEV_ENTRY_MODE_SHIFT;

	pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;





	write_lock_irqsave(&amd_iommu_devtable_lock, flags);

	write_lock_irqsave(&amd_iommu_devtable_lock, flags);

	amd_iommu_dev_table[devid].data[0] = pte_root;

	amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);

	amd_iommu_dev_table[devid].data[1] = pte_root >> 32;

	amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);

	amd_iommu_dev_table[devid].data[2] = domain->id;

	amd_iommu_dev_table[devid].data[2] = domain->id;





	amd_iommu_pd_table[devid] = domain;

	amd_iommu_pd_table[devid] = domain;

include/asm-x86/amd_iommu_types.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -130,6 +130,8 @@ 
#define DEV_ENTRY_NMI_PASS      0xba

#define DEV_ENTRY_NMI_PASS      0xba

#define DEV_ENTRY_LINT0_PASS    0xbe

#define DEV_ENTRY_LINT0_PASS    0xbe

#define DEV_ENTRY_LINT1_PASS    0xbf

#define DEV_ENTRY_LINT1_PASS    0xbf

#define DEV_ENTRY_MODE_MASK	0x07

#define DEV_ENTRY_MODE_SHIFT	0x09





/* constants to configure the command buffer */

/* constants to configure the command buffer */

#define CMD_BUFFER_SIZE    8192

#define CMD_BUFFER_SIZE    8192
@@ -159,6 +161,7 @@ 
#define IOMMU_MAP_SIZE_L3 (1ULL << 39)

#define IOMMU_MAP_SIZE_L3 (1ULL << 39)





#define IOMMU_PTE_P  (1ULL << 0)

#define IOMMU_PTE_P  (1ULL << 0)

#define IOMMU_PTE_TV (1ULL << 1)

#define IOMMU_PTE_U  (1ULL << 59)

#define IOMMU_PTE_U  (1ULL << 59)

#define IOMMU_PTE_FC (1ULL << 60)

#define IOMMU_PTE_FC (1ULL << 60)

#define IOMMU_PTE_IR (1ULL << 61)

#define IOMMU_PTE_IR (1ULL << 61)