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Commit 38cf9db9 authored Sep 11, 2020 by qctecmdr Committed by Gerrit - the friendly Code Review server Sep 11, 2020

Merge "ARM: dts: msm: Update PCIe1 PHY settings to v1.06 for lahaina"

parents 697a88b5 def53353

qcom/lahaina-pcie.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -336,7 +336,7 @@
		qcom,slv-addr-space-size = <0x20000000>;
		qcom,ep-latency = <10>;

		qcom,pcie-phy-ver = <1104>;
		qcom,pcie-phy-ver = <1106>;
		qcom,phy-status-offset = <0x214>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x240>;
		@@ -408,12 +408,16 @@
		0x1978 0x5c 0x0
		0x197c 0x34 0x0
		0x1980 0xa6 0x0
		0x10cc 0xf0 0x0
		0x18cc 0xf0 0x0
		0x10d8 0x0f 0x0
		0x18d8 0x0f 0x0
		0x10dc 0x00 0x0
		0x18dc 0x00 0x0
		0x11a4 0x38 0x0
		0x19a4 0x38 0x0
		0x0e3c 0x1d 0x0
		0x163c 0x1d 0x0
		0x0e40 0x0c 0x0
		0x1640 0x0c 0x0
		0x1190 0x34 0x0
		@@ -423,7 +427,7 @@
		0x1050 0x08 0x0
		0x1850 0x08 0x0
		0x02dc 0x05 0x0
		0x0388 0x88 0x0
		0x0388 0x77 0x0
		0x0398 0x0b 0x0
		0x03e0 0x0f 0x0
		0x060c 0x1d 0x0