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Commit 38b96be6 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: camera: isp: Add YUV support in CAMIF" into camera-kernel.lnx.4.0

parents d12abfb4 472804a0

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+53 −15
Original line number Diff line number Diff line
@@ -27,11 +27,11 @@ 


/* TPG VC/DT values */

#define CAM_IFE_CSID_TPG_VC_VAL                        0xA

#define CAM_IFE_CSID_TPG_DT_VAL                        0x2B

#define CAM_IFE_CSID_TPG_YUV_DT_VAL                    0x1e

#define CAM_IFE_CSID_TPG_RGB_DT_VAL                    0x2B



/* CSIPHY TPG VC/DT values */

#define CAM_IFE_CPHY_TPG_VC_VAL                         0x0

#define CAM_IFE_CPHY_TPG_DT_VAL                         0x2B



/* Timeout values in usec */

#define CAM_IFE_CSID_TIMEOUT_SLEEP_US                  1000
@@ -76,6 +76,7 @@ static int cam_ife_csid_is_ipp_ppp_format_supported( 
	case CAM_FORMAT_DPCM_14_8_14:

	case CAM_FORMAT_DPCM_14_10_14:

	case CAM_FORMAT_DPCM_12_10_12:

	case CAM_FORMAT_YUV422:

		rc = 0;

		break;

	default:
@@ -254,6 +255,10 @@ static int cam_ife_csid_get_format_rdi( 
		*decode_fmt  = 0xD;

		*plain_fmt = 0x1;

		break;

	case CAM_FORMAT_YUV422:

		*decode_fmt  = 0x1;

		*plain_fmt = 0x0;

		break;

	default:

		rc = -EINVAL;

		break;
@@ -332,6 +337,10 @@ static int cam_ife_csid_get_format_ipp_ppp( 
		*decode_fmt  = 0xD;

		*plain_fmt = 0x1;

		break;

	case CAM_FORMAT_YUV422:

		*decode_fmt  = 0x1;

		*plain_fmt = 0;

		break;

	default:

		CAM_ERR(CAM_ISP, "Unsupported format %d",

			in_format);
@@ -992,9 +1001,11 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 


		/* Below code is executed only for TPG in_res type */

		csid_hw->csi2_rx_cfg.phy_sel = 0;

		if (cid_reserv->in_port->format >

		    CAM_FORMAT_MIPI_RAW_16) {

			CAM_ERR(CAM_ISP, " Wrong TPG format");

		if ((cid_reserv->in_port->format != CAM_FORMAT_YUV422) &&

			(cid_reserv->in_port->format >

			    CAM_FORMAT_MIPI_RAW_16)) {

			CAM_ERR(CAM_ISP, " Wrong TPG format %d",

				cid_reserv->in_port->format);

			rc = -EINVAL;

			goto end;

		}
@@ -1300,15 +1311,30 @@ int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, 
		reserve->in_port->line_start, reserve->in_port->line_stop,

		path_data->crop_enable, path_data->hblank_cnt);



	if ((reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_CPHY_TPG_0) ||

		(reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_CPHY_TPG_1) ||

		(reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_CPHY_TPG_2)) {

		path_data->dt = CAM_IFE_CPHY_TPG_DT_VAL;



	switch (reserve->in_port->res_type) {



	case CAM_ISP_IFE_IN_RES_CPHY_TPG_0:

	case CAM_ISP_IFE_IN_RES_CPHY_TPG_1:

	case CAM_ISP_IFE_IN_RES_CPHY_TPG_2:

		path_data->vc = CAM_IFE_CPHY_TPG_VC_VAL;

	} else if (reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) {

		path_data->dt = CAM_IFE_CSID_TPG_DT_VAL;



		if (path_data->in_format == CAM_FORMAT_YUV422)

			path_data->dt = CAM_IFE_CSID_TPG_YUV_DT_VAL;

		else

			path_data->dt = CAM_IFE_CSID_TPG_RGB_DT_VAL;

		break;



	case CAM_ISP_IFE_IN_RES_TPG:

		path_data->vc = CAM_IFE_CSID_TPG_VC_VAL;

	} else {



		if (path_data->in_format == CAM_FORMAT_YUV422)

			path_data->dt = CAM_IFE_CSID_TPG_YUV_DT_VAL;

		else

			path_data->dt = CAM_IFE_CSID_TPG_RGB_DT_VAL;

		break;



	default:

		path_data->dt = reserve->in_port->dt[0];

		path_data->vc = reserve->in_port->vc[0];

		if (reserve->in_port->num_valid_vc_dt) {
@@ -1316,6 +1342,7 @@ int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, 
			path_data->vc1 = reserve->in_port->vc[1];

			path_data->is_valid_vc1_dt1 = 1;

		}

		break;

	}



	if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) {
@@ -1691,6 +1718,7 @@ static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, 
	const struct cam_ife_csid_reg_offset *csid_reg;

	struct cam_hw_soc_info               *soc_info;

	uint32_t val = 0;

	uint32_t dt, in_format, test_pattern;



	csid_reg = csid_hw->csid_info->csid_reg;

	soc_info = &csid_hw->hw_info->soc_info;
@@ -1716,14 +1744,24 @@ static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, 
	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->tpg_reg->csid_tpg_dt_n_cfg_0_addr);



	cam_io_w_mb(CAM_IFE_CSID_TPG_DT_VAL, soc_info->reg_map[0].mem_base +

	if (csid_hw->tpg_cfg.in_format == CAM_FORMAT_YUV422) {

		in_format = 0x2;

		dt = CAM_IFE_CSID_TPG_YUV_DT_VAL;

		test_pattern = 0x4;

	} else {

		in_format = csid_hw->tpg_cfg.in_format;

		dt = CAM_IFE_CSID_TPG_RGB_DT_VAL;

		test_pattern = csid_hw->tpg_cfg.test_pattern;

	}



	cam_io_w_mb(dt, soc_info->reg_map[0].mem_base +

		csid_reg->tpg_reg->csid_tpg_dt_n_cfg_1_addr);



	/*

	 * in_format is the same as the input resource format.

	 * it is one larger than the register spec format.

	 */

	val = ((csid_hw->tpg_cfg.in_format - 1) << 16) | 0x8;

	val = ((in_format - 1) << 16) | 0x8;

	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->tpg_reg->csid_tpg_dt_n_cfg_2_addr);
@@ -1732,7 +1770,7 @@ static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, 
	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

		csid_reg->tpg_reg->csid_tpg_color_bars_cfg_addr);

	/* config pix pattern */

	cam_io_w_mb(csid_hw->tpg_cfg.test_pattern,

	cam_io_w_mb(test_pattern,

		soc_info->reg_map[0].mem_base +

		csid_reg->tpg_reg->csid_tpg_common_gen_cfg_addr);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

+1 −0
Original line number Diff line number Diff line
@@ -1103,6 +1103,7 @@ static int cam_vfe_bus_ver3_acquire_wm( 
		case CAM_FORMAT_MIPI_RAW_20:

		case CAM_FORMAT_PLAIN128:

		case CAM_FORMAT_PLAIN32_20:

		case CAM_FORMAT_YUV422:

			rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH;

			rsrc_data->height = 0;

			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

+15 −4
Original line number Diff line number Diff line
@@ -169,7 +169,8 @@ static int cam_vfe_camif_ver3_err_irq_top_half( 
	return rc;

}



static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern)

static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern,

	uint32_t *input_pp_fmt)

{

	int rc;
@@ -178,11 +179,16 @@ static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern) 
	case CAM_ISP_PATTERN_BAYER_GRGRGR:

	case CAM_ISP_PATTERN_BAYER_BGBGBG:

	case CAM_ISP_PATTERN_BAYER_GBGBGB:

		rc = 0;

		*input_pp_fmt = CAM_ISP_PP_INPUT_BAYER_FMT;

		break;



	case CAM_ISP_PATTERN_YUV_YCBYCR:

	case CAM_ISP_PATTERN_YUV_YCRYCB:

	case CAM_ISP_PATTERN_YUV_CBYCRY:

	case CAM_ISP_PATTERN_YUV_CRYCBY:

		rc = 0;

		*input_pp_fmt = CAM_ISP_PP_INPUT_YUV_FMT;

		break;

	default:

		CAM_ERR(CAM_ISP, "Error, Invalid pix pattern:%d", pattern);
@@ -256,7 +262,8 @@ int cam_vfe_camif_ver3_acquire_resource( 
	acquire_data = (struct cam_vfe_acquire_args *)acquire_param;



	rc = cam_vfe_camif_ver3_validate_pix_pattern(

		acquire_data->vfe_in.in_port->test_pattern);

		acquire_data->vfe_in.in_port->test_pattern,

		&camif_data->cam_common_cfg.input_pp_fmt);



	if (rc) {

		CAM_ERR(CAM_ISP, "Validate pix pattern failed, rc = %d", rc);
@@ -285,10 +292,11 @@ int cam_vfe_camif_ver3_acquire_resource( 
		camif_data->dual_hw_idx = acquire_data->vfe_in.dual_hw_idx;



	CAM_DBG(CAM_ISP,

		"VFE:%d CAMIF pix_pattern:%d dsp_mode=%d is_dual:%d dual_hw_idx:%d",

		"VFE:%d CAMIF pix_pattern:%d dsp_mode=%d is_dual:%d dual_hw_idx:%d format = %d",

		camif_res->hw_intf->hw_idx,

		camif_data->pix_pattern, camif_data->dsp_mode,

		camif_data->is_dual, camif_data->dual_hw_idx);

		camif_data->is_dual, camif_data->dual_hw_idx,

		acquire_data->vfe_in.in_port->format);



	return rc;

}
@@ -445,6 +453,9 @@ static int cam_vfe_camif_ver3_resource_start( 
		CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST;

	val |= (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) <<

		CAM_SHIFT_TOP_CORE_CFG_INPUTMUX_PP;

	val |= (rsrc_data->cam_common_cfg.input_pp_fmt & 0x3) <<

		CAM_SHIFT_TOP_CORE_CFG_INPUT_PP_FMT;





	if (rsrc_data->is_fe_enabled && !rsrc_data->is_offline)

		val |= 0x2 << rsrc_data->reg_data->operating_mode_shift;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h

+3 −0
Original line number Diff line number Diff line
@@ -9,6 +9,9 @@ 
#include "cam_isp_hw.h"

#include "cam_vfe_top.h"



#define CAM_ISP_PP_INPUT_BAYER_FMT 0

#define CAM_ISP_PP_INPUT_YUV_FMT 1



struct cam_vfe_camif_ver3_pp_clc_reg {

	uint32_t     hw_version;

	uint32_t     hw_status;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#define CAM_SHIFT_TOP_CORE_CFG_DISP_DS16_R2PD    28

#define CAM_SHIFT_TOP_CORE_CFG_DISP_DS4_R2PD     27

#define CAM_SHIFT_TOP_CORE_CFG_DSP_STREAMING     25

#define CAM_SHIFT_TOP_CORE_CFG_INPUT_PP_FMT      14

#define CAM_SHIFT_TOP_CORE_CFG_STATS_IHIST       10

#define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BE       9

#define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST    8
@@ -75,6 +76,7 @@ struct cam_vfe_camif_common_cfg { 
	uint32_t     hdr_bhist_src_sel;

	uint32_t     input_mux_sel_pdaf;

	uint32_t     input_mux_sel_pp;

	uint32_t     input_pp_fmt;

};



struct cam_vfe_top_ver3_hw_info {