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Commit 388412db authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: Enable RTB on sdxlemur"

parents 1549f8a0 4fd9da81

arch/arm/configs/vendor/sdxlemur-debug.config

+2 −0
Original line number Original line Diff line number Diff line
@@ -55,3 +55,5 @@ CONFIG_VFAT_FS=y 
CONFIG_MHI_BUS=y

CONFIG_MHI_BUS=y

CONFIG_MHI_DEBUG=y

CONFIG_MHI_DEBUG=y

CONFIG_MHI_UCI=y

CONFIG_MHI_UCI=y

CONFIG_QCOM_RTB=y

CONFIG_QCOM_RTB_QGKI=y

arch/arm/include/asm/io.h

+23 −0
Original line number Original line Diff line number Diff line
@@ -96,6 +96,18 @@ static inline void __raw_writel(u32 val, volatile void __iomem *addr) 
		     : : "Qo" (*(volatile u32 __force *)addr), "r" (val));

		     : : "Qo" (*(volatile u32 __force *)addr), "r" (val));

}

}





#define __raw_writeq __raw_writeq

static inline void __raw_writeq(u64 val, volatile void __iomem *addr)

{

	register u64 v asm ("r2");



	v = val;



	asm volatile("strd %1, %0"

		     : "+Qo" (*(volatile u64 __force *)addr)

		     : "r" (v));

}



#define __raw_readb __raw_readb

#define __raw_readb __raw_readb

static inline u8 __raw_readb(const volatile void __iomem *addr)

static inline u8 __raw_readb(const volatile void __iomem *addr)

{

{
@@ -116,6 +128,17 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) 
	return val;

	return val;

}

}





#define __raw_readq __raw_readq

static inline u64 __raw_readq(const volatile void __iomem *addr)

{

	register u64 val asm ("r2");



	asm volatile("ldrd %1, %0"

		     : "+Qo" (*(volatile u64 __force *)addr),

		       "=r" (val));

	return val;

}



/*

/*

 * Architecture ioremap implementation.

 * Architecture ioremap implementation.

 */

 */