Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 383bee6b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
  PCI: Ensure we re-enable devices on resume
  x86/PCI: parse additional host bridge window resource types
  PCI: revert broken device warning
  PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset
  x86/PCI: ignore Consumer/Producer bit in ACPI window descriptions
parents b39c8be6 cc2893b6

arch/x86/pci/acpi.c

+37 −7
Original line number Diff line number Diff line
@@ -66,15 +66,45 @@ resource_to_addr(struct acpi_resource *resource, 
			struct acpi_resource_address64 *addr)

{

	acpi_status status;



	struct acpi_resource_memory24 *memory24;

	struct acpi_resource_memory32 *memory32;

	struct acpi_resource_fixed_memory32 *fixed_memory32;



	memset(addr, 0, sizeof(*addr));

	switch (resource->type) {

	case ACPI_RESOURCE_TYPE_MEMORY24:

		memory24 = &resource->data.memory24;

		addr->resource_type = ACPI_MEMORY_RANGE;

		addr->minimum = memory24->minimum;

		addr->address_length = memory24->address_length;

		addr->maximum = addr->minimum + addr->address_length - 1;

		return AE_OK;

	case ACPI_RESOURCE_TYPE_MEMORY32:

		memory32 = &resource->data.memory32;

		addr->resource_type = ACPI_MEMORY_RANGE;

		addr->minimum = memory32->minimum;

		addr->address_length = memory32->address_length;

		addr->maximum = addr->minimum + addr->address_length - 1;

		return AE_OK;

	case ACPI_RESOURCE_TYPE_FIXED_MEMORY32:

		fixed_memory32 = &resource->data.fixed_memory32;

		addr->resource_type = ACPI_MEMORY_RANGE;

		addr->minimum = fixed_memory32->address;

		addr->address_length = fixed_memory32->address_length;

		addr->maximum = addr->minimum + addr->address_length - 1;

		return AE_OK;

	case ACPI_RESOURCE_TYPE_ADDRESS16:

	case ACPI_RESOURCE_TYPE_ADDRESS32:

	case ACPI_RESOURCE_TYPE_ADDRESS64:

		status = acpi_resource_to_address64(resource, addr);

		if (ACPI_SUCCESS(status) &&

		    (addr->resource_type == ACPI_MEMORY_RANGE ||

		    addr->resource_type == ACPI_IO_RANGE) &&

	    addr->address_length > 0 &&

	    addr->producer_consumer == ACPI_PRODUCER) {

		    addr->address_length > 0) {

			return AE_OK;

		}

		break;

	}

	return AE_ERROR;

}

drivers/pci/pci.c

+1 −5
Original line number Diff line number Diff line
@@ -679,7 +679,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 
 */

int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)

{

	return state > PCI_D0 ?

	return state >= PCI_D0 ?

			pci_platform_power_transition(dev, state) : -EINVAL;

}

EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
@@ -716,10 +716,6 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 
		 */

		return 0;



	/* Check if we're already there */

	if (dev->current_state == state)

		return 0;



	__pci_start_power_transition(dev, state);



	/* This device is quirked not to be put into D3, so

drivers/pci/pcie/aer/aerdrv.c

+8 −2
Original line number Diff line number Diff line
@@ -244,11 +244,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 


	/* Assert Secondary Bus Reset */

	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);

	p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET;

	p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;

	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);



	/*

	 * we should send hot reset message for 2ms to allow it time to

	 * propogate to all downstream ports

	 */

	msleep(2);



	/* De-assert Secondary Bus Reset */

	p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET;

	p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;

	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);



	/*

drivers/pci/probe.c

+7 −16
Original line number Diff line number Diff line
@@ -174,19 +174,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 
	pci_read_config_dword(dev, pos, &sz);

	pci_write_config_dword(dev, pos, l);



	if (!sz)

		goto fail;	/* BAR not implemented */



	/*

	 * All bits set in sz means the device isn't working properly.

	 * If it's a memory BAR or a ROM, bit 0 must be clear; if it's

	 * an io BAR, bit 1 must be clear.

	 * If the BAR isn't implemented, all bits must be 0.  If it's a

	 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit

	 * 1 must be clear.

	 */

	if (sz == 0xffffffff) {

		dev_err(&dev->dev, "reg %x: invalid size %#x; broken device?\n",

			pos, sz);

	if (!sz || sz == 0xffffffff)

		goto fail;

	}



	/*

	 * I don't know how l can have all bits set.  Copied from old code.
@@ -249,17 +244,13 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 
				   pos, res);

		}

	} else {

		u32 size = pci_size(l, sz, mask);

		sz = pci_size(l, sz, mask);



		if (!size) {

			dev_err(&dev->dev, "reg %x: invalid size "

			        "(l %#x sz %#x mask %#x); broken device?",

				pos, l, sz, mask);

		if (!sz)

			goto fail;

		}



		res->start = l;

		res->end = l + size;

		res->end = l + sz;



		dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);

	}