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Commit 37c922d8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "platform: msm-geni-se: Add missing fixes from msm-4.19"

parents a2ce4cbb e21fd7a3

drivers/platform/msm/msm-geni-se.c

+10 −4
Original line number Diff line number Diff line
@@ -326,14 +326,16 @@ static int geni_se_select_fifo_mode(void __iomem *base) 
			M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);

		common_geni_s_irq_en |= S_CMD_DONE_EN;

	}



	if (proto == I3C)

		common_geni_m_irq_en |=  (M_GP_SYNC_IRQ_0_EN | M_SEC_IRQ_EN);



	geni_dma_mode &= ~GENI_DMA_MODE_EN;



	geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);

	geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN);

	geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);



	if (proto == I3C)

		geni_write_reg(0x3, base, GENI_I3C_IBI_LEGACY);

	return 0;

}
@@ -1502,6 +1504,8 @@ void geni_se_dump_dbg_regs(struct se_geni_rsc *rsc, void __iomem *base, 
{

	u32 m_cmd0 = 0;

	u32 m_irq_status = 0;

	u32 s_cmd0 = 0;

	u32 s_irq_status = 0;

	u32 geni_status = 0;

	u32 geni_ios = 0;

	u32 dma_rx_irq = 0;
@@ -1528,10 +1532,12 @@ void geni_se_dump_dbg_regs(struct se_geni_rsc *rsc, void __iomem *base, 
	}

	m_cmd0 = geni_read_reg(base, SE_GENI_M_CMD0);

	m_irq_status = geni_read_reg(base, SE_GENI_M_IRQ_STATUS);

	s_cmd0 = geni_read_reg(base, SE_GENI_S_CMD0);

	s_irq_status = geni_read_reg(base, SE_GENI_S_IRQ_STATUS);

	geni_status = geni_read_reg(base, SE_GENI_STATUS);

	geni_ios = geni_read_reg(base, SE_GENI_IOS);

	dma_rx_irq = geni_read_reg(base, SE_DMA_TX_IRQ_STAT);

	dma_tx_irq = geni_read_reg(base, SE_DMA_RX_IRQ_STAT);

	dma_tx_irq = geni_read_reg(base, SE_DMA_TX_IRQ_STAT);

	dma_rx_irq = geni_read_reg(base, SE_DMA_RX_IRQ_STAT);

	rx_fifo_status = geni_read_reg(base, SE_GENI_RX_FIFO_STATUS);

	tx_fifo_status = geni_read_reg(base, SE_GENI_TX_FIFO_STATUS);

	se_dma_dbg = geni_read_reg(base, SE_DMA_DEBUG_REG0);

include/linux/msm-geni-se.h

+3 −7
Original line number Diff line number Diff line
@@ -69,9 +69,8 @@ struct se_geni_rsc { 
	int	clk_freq_out;

};



/* Offset of QUPV3 Hardware Version Register */

#define QUPV3_HW_VER (0x4)

#define PINCTRL_DEFAULT	"default"

#define PINCTRL_ACTIVE	"active"

#define PINCTRL_SLEEP	"sleep"



#define KHz(freq) (1000 * (freq))
@@ -116,13 +115,13 @@ struct se_geni_rsc { 
#define SE_GENI_IOS			(0x908)

#define SE_GENI_M_GP_LENGTH		(0x910)

#define SE_GENI_S_GP_LENGTH		(0x914)

#define GENI_I3C_IBI_LEGACY		(0xA9c)

#define SE_GSI_EVENT_EN			(0xE18)

#define SE_IRQ_EN			(0xE1C)

#define SE_HW_PARAM_0			(0xE24)

#define SE_HW_PARAM_1			(0xE28)

#define SE_DMA_GENERAL_CFG		(0xE30)

#define SE_DMA_DEBUG_REG0		(0xE40)

#define QUPV3_HW_VER			(0x4)



/* GENI_OUTPUT_CTRL fields */

#define DEFAULT_IO_OUTPUT_CTRL_MSK	(GENMASK(6, 0))
@@ -260,10 +259,6 @@ struct se_geni_rsc { 
#define GENI_M_EVENT_EN		(BIT(2))

#define GENI_S_EVENT_EN		(BIT(3))



/* GENI_I3C_IBI_LEGACY fields */

#define I3C_IBI_LEGACY_EN	(BIT(0))

#define I3C_IBI_LEGACY_PORTS_EN	(BIT(1))



/* SE_GENI_IOS fields */

#define IO2_DATA_IN		(BIT(1))

#define RX_DATA_IN		(BIT(0))
@@ -279,6 +274,7 @@ struct se_geni_rsc { 
#define TX_FIFO_WIDTH_SHFT	(24)

#define TX_FIFO_DEPTH_MSK	(GENMASK(21, 16))

#define TX_FIFO_DEPTH_SHFT	(16)

#define GEN_I3C_IBI_CTRL	(BIT(7))



/* SE_HW_PARAM_1 fields */

#define RX_FIFO_WIDTH_MSK	(GENMASK(29, 24))