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Commit 37c8f6e6 authored Oct 24, 2018 by David Francis Committed by Alex Deucher Nov 19, 2018

drm/amd/display: Clean up dp_blank functions



[Why]
Unused variable "refresh" and incorrect comment formatting

[How]
Remove variable, reindent comments

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 4b594b8d

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

+10 −13

Original line number	Original line	Diff line number	Diff line
	@@ -908,7 +908,6 @@ static void dce110_stream_encoder_dp_blank(
	struct stream_encoder *enc)		struct stream_encoder *enc)
	{		{
	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);		struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
	uint32_t retries = 0;
	uint32_t reg1 = 0;		uint32_t reg1 = 0;
	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;		uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;

	@@ -943,8 +942,6 @@ static void dce110_stream_encoder_dp_blank(
	0,		0,
	10, max_retries);		10, max_retries);

	ASSERT(retries <= max_retries);

	/* Tell the DP encoder to ignore timing from CRTC, must be done after		/* Tell the DP encoder to ignore timing from CRTC, must be done after
	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is		* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
	* complete, stream status will be stuck in video stream enabled state,		* complete, stream status will be stuck in video stream enabled state,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

+0 −3

Original line number	Original line	Diff line number	Diff line
	@@ -766,7 +766,6 @@ void enc1_stream_encoder_dp_blank(
	struct stream_encoder *enc)		struct stream_encoder *enc)
	{		{
	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);		struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
	uint32_t retries = 0;
	uint32_t reg1 = 0;		uint32_t reg1 = 0;
	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;		uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;

	@@ -803,8 +802,6 @@ void enc1_stream_encoder_dp_blank(
	0,		0,
	10, max_retries);		10, max_retries);

	ASSERT(retries <= max_retries);

	/* Tell the DP encoder to ignore timing from CRTC, must be done after		/* Tell the DP encoder to ignore timing from CRTC, must be done after
	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is		* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
	* complete, stream status will be stuck in video stream enabled state,		* complete, stream status will be stuck in video stream enabled state,