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Commit 37c045d2 authored by Jacopo Mondi's avatar Jacopo Mondi Committed by Shawn Guo
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ARM: dts: imx6qdl: Add Engicam i.Core 1.5 MX6 



The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock
provider for the ethernet's PHY interface. Adjust the FEC ptp clock to
reference CLK_ENET_REF clock source, and set SION bit of
MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin.

The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single
place differences between version '1.0' and '1.5' of the module.

Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarJacopo Mondi <jacopo@jmondi.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent cc07fd3c

arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi

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+34 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>

 */



#include "imx6qdl-icore.dtsi"



&iomuxc {

	pinctrl_enet: enetgrp {

		fsl,pins = <

			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0

			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0b0

			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0

			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0

			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0

			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0

			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0

			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0

		>;

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet>;

	phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;

	clocks = <&clks IMX6QDL_CLK_ENET>,

		 <&clks IMX6QDL_CLK_ENET>,

		 <&clks IMX6QDL_CLK_ENET_REF>;

	phy-mode = "rmii";

	status = "okay";

};