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Commit 37903b5e authored by Christian König's avatar Christian König
Browse files

drm/radeon: sync page table updates



Only necessary if we don't use the same engine for buffer moves and table updates.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
parent 2f93dc32
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+7 −2
Original line number Original line Diff line number Diff line
@@ -585,7 +585,8 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
{
{
	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;


	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
	struct radeon_bo *pd = vm->page_directory;
	uint64_t pd_addr = radeon_bo_gpu_offset(pd);
	uint64_t last_pde = ~0, last_pt = ~0;
	uint64_t last_pde = ~0, last_pt = ~0;
	unsigned count = 0, pt_idx, ndw;
	unsigned count = 0, pt_idx, ndw;
	struct radeon_ib ib;
	struct radeon_ib ib;
@@ -642,6 +643,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
					incr, R600_PTE_VALID);
					incr, R600_PTE_VALID);


	if (ib.length_dw != 0) {
	if (ib.length_dw != 0) {
		radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
		radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
		radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
		r = radeon_ib_schedule(rdev, &ib, NULL);
		r = radeon_ib_schedule(rdev, &ib, NULL);
		if (r) {
		if (r) {
@@ -689,15 +691,18 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
	/* walk over the address space and update the page tables */
	/* walk over the address space and update the page tables */
	for (addr = start; addr < end; ) {
	for (addr = start; addr < end; ) {
		uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
		uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
		struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
		unsigned nptes;
		unsigned nptes;
		uint64_t pte;
		uint64_t pte;


		radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);

		if ((addr & ~mask) == (end & ~mask))
		if ((addr & ~mask) == (end & ~mask))
			nptes = end - addr;
			nptes = end - addr;
		else
		else
			nptes = RADEON_VM_PTE_COUNT - (addr & mask);
			nptes = RADEON_VM_PTE_COUNT - (addr & mask);


		pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo);
		pte = radeon_bo_gpu_offset(pt);
		pte += (addr & mask) * 8;
		pte += (addr & mask) * 8;


		if ((last_pte + 8 * count) != pte) {
		if ((last_pte + 8 * count) != pte) {