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Commit 377007c9 authored by Chris Goldsworthy's avatar Chris Goldsworthy
Browse files

iommu/arm-smmu: bypass hypervisor and read sync/inval status register 



ARM_SMMU_STATS_SYNC_INV_TBU_ACK has been made accessible to HLOS 1, read
it's value directly instead of making an SCM call to retrieve it.

Change-Id: I34f5d18e9a5bdee6857f2398974257a49b1f54fb
Signed-off-by: default avatarChris Goldsworthy <cgoldswo@codeaurora.org>
parent 55b8beb9

drivers/iommu/arm-smmu.c

+4 −4
Original line number Diff line number Diff line
@@ -69,8 +69,6 @@ 
#define TLB_LOOP_TIMEOUT		500000	/* 500ms */

#define TLB_SPIN_COUNT			10



#define ARM_SMMU_IMPL_DEF0(smmu) \

	((smmu)->base + (2 * (1 << (smmu)->pgshift)))

#define ARM_SMMU_IMPL_DEF1(smmu) \

	((smmu)->base + (6 * (1 << (smmu)->pgshift)))
@@ -883,8 +881,10 @@ static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, 
		}

		udelay(delay);

	}

	sync_inv_ack = scm_io_read((unsigned long)(smmu->phys_addr +

				     ARM_SMMU_STATS_SYNC_INV_TBU_ACK));



	sync_inv_ack = arm_smmu_readl(smmu,

				      ARM_SMMU_IMPL_DEF0,

				      ARM_SMMU_STATS_SYNC_INV_TBU_ACK);

	tbu_pwr_status = scm_io_read((unsigned long)(smmu->phys_addr +

				     ARM_SMMU_TBU_PWR_STATUS));

	sync_inv_progress = scm_io_read((unsigned long)(smmu->phys_addr +

drivers/iommu/arm-smmu.h

+7 −1
Original line number Diff line number Diff line
@@ -221,8 +221,13 @@ enum arm_smmu_cbar_type { 
#define ARM_SMMU_CB_TLBSTATUS		0x7f4

#define TLBSTATUS_SACTIVE		BIT(0)

#define ARM_SMMU_CB_ATS1PR		0x800

#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x25dc



/* Implementation Defined Register Space 0 registers*/

/* Relative to IMPL_DEF_0 page */

#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x5dc

/* Relative to SMMU_BASE */

#define ARM_SMMU_TBU_PWR_STATUS         0x2204

/* Relative SMMU_BASE */

#define ARM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x2670



#define ARM_SMMU_CB_ATSR		0x8f0
@@ -470,6 +475,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, 


#define ARM_SMMU_GR0		0

#define ARM_SMMU_GR1		1

#define ARM_SMMU_IMPL_DEF0	2

#define ARM_SMMU_CB(s, n)	((s)->numpage + (n))



#define arm_smmu_gr0_read(s, o)		\