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Commit 3760f76c authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdgpu: Move IH clientid defs to separate file 



This is preparation for sharing client ID definitions
between amdgpu and amdkfd

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarChunming Zhou <david1.zhou@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e36ec859

drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h

+2 −41
Original line number Diff line number Diff line
@@ -25,51 +25,12 @@ 
#define __AMDGPU_IH_H__



#include <linux/chash.h>

#include "soc15_ih_clientid.h"



struct amdgpu_device;

 /*

  * vega10+ IH clients

 */

enum amdgpu_ih_clientid

{

    AMDGPU_IH_CLIENTID_IH	    = 0x00,

    AMDGPU_IH_CLIENTID_ACP	    = 0x01,

    AMDGPU_IH_CLIENTID_ATHUB	    = 0x02,

    AMDGPU_IH_CLIENTID_BIF	    = 0x03,

    AMDGPU_IH_CLIENTID_DCE	    = 0x04,

    AMDGPU_IH_CLIENTID_ISP	    = 0x05,

    AMDGPU_IH_CLIENTID_PCIE0	    = 0x06,

    AMDGPU_IH_CLIENTID_RLC	    = 0x07,

    AMDGPU_IH_CLIENTID_SDMA0	    = 0x08,

    AMDGPU_IH_CLIENTID_SDMA1	    = 0x09,

    AMDGPU_IH_CLIENTID_SE0SH	    = 0x0a,

    AMDGPU_IH_CLIENTID_SE1SH	    = 0x0b,

    AMDGPU_IH_CLIENTID_SE2SH	    = 0x0c,

    AMDGPU_IH_CLIENTID_SE3SH	    = 0x0d,

    AMDGPU_IH_CLIENTID_SYSHUB	    = 0x0e,

    AMDGPU_IH_CLIENTID_THM	    = 0x0f,

    AMDGPU_IH_CLIENTID_UVD	    = 0x10,

    AMDGPU_IH_CLIENTID_VCE0	    = 0x11,

    AMDGPU_IH_CLIENTID_VMC	    = 0x12,

    AMDGPU_IH_CLIENTID_XDMA	    = 0x13,

    AMDGPU_IH_CLIENTID_GRBM_CP	    = 0x14,

    AMDGPU_IH_CLIENTID_ATS	    = 0x15,

    AMDGPU_IH_CLIENTID_ROM_SMUIO    = 0x16,

    AMDGPU_IH_CLIENTID_DF	    = 0x17,

    AMDGPU_IH_CLIENTID_VCE1	    = 0x18,

    AMDGPU_IH_CLIENTID_PWR	    = 0x19,

    AMDGPU_IH_CLIENTID_UTCL2	    = 0x1b,

    AMDGPU_IH_CLIENTID_EA	    = 0x1c,

    AMDGPU_IH_CLIENTID_UTCL2LOG	    = 0x1d,

    AMDGPU_IH_CLIENTID_MP0	    = 0x1e,

    AMDGPU_IH_CLIENTID_MP1	    = 0x1f,



    AMDGPU_IH_CLIENTID_MAX,



    AMDGPU_IH_CLIENTID_VCN	    = AMDGPU_IH_CLIENTID_UVD

};



#define AMDGPU_IH_CLIENTID_LEGACY 0

#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX



#define AMDGPU_PAGEFAULT_HASH_BITS 8

struct amdgpu_retryfault_hashtable {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1261,23 +1261,23 @@ static int gfx_v9_0_sw_init(void *handle) 
	adev->gfx.mec.num_queue_per_pipe = 8;



	/* KIQ event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);

	if (r)

		return r;



	/* EOP Event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);

	if (r)

		return r;



	/* Privileged reg */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,

			      &adev->gfx.priv_reg_irq);

	if (r)

		return r;



	/* Privileged inst */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,

			      &adev->gfx.priv_inst_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+2 −2
Original line number Diff line number Diff line
@@ -861,9 +861,9 @@ static int gmc_v9_0_sw_init(void *handle) 
	}



	/* This interrupt is VMC page fault.*/

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,

				&adev->gmc.vm_fault);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,

				&adev->gmc.vm_fault);



	if (r)

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

+2 −2
Original line number Diff line number Diff line
@@ -329,11 +329,11 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev) 
{

	int r;



	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);

	if (r)

		return r;



	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);

	if (r) {

		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);

		return r;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1172,13 +1172,13 @@ static int sdma_v4_0_sw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* SDMA trap event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,

			      &adev->sdma.trap_irq);

	if (r)

		return r;



	/* SDMA trap event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,

			      &adev->sdma.trap_irq);

	if (r)

		return r;
@@ -1333,7 +1333,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 
{

	DRM_DEBUG("IH: SDMA trap\n");

	switch (entry->client_id) {

	case AMDGPU_IH_CLIENTID_SDMA0:

	case SOC15_IH_CLIENTID_SDMA0:

		switch (entry->ring_id) {

		case 0:

			amdgpu_fence_process(&adev->sdma.instance[0].ring);
@@ -1349,7 +1349,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 
			break;

		}

		break;

	case AMDGPU_IH_CLIENTID_SDMA1:

	case SOC15_IH_CLIENTID_SDMA1:

		switch (entry->ring_id) {

		case 0:

			amdgpu_fence_process(&adev->sdma.instance[1].ring);