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Commit 36ea73cb authored by Bich HEMON's avatar Bich HEMON Committed by Wolfram Sang
Browse files

dt-bindings: i2c: stm32: update optional properties for stm32h7/stm32mp1 



Add STM32H7 and STM32MP1 in the list of compatible socs for each
optional property.

Signed-off-by: default avatarBich Hemon <bich.hemon@st.com>
Reviewed-by: default avatarPierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 472ec0ce

Documentation/devicetree/bindings/i2c/i2c-stm32.txt

+9 −8
Original line number Original line Diff line number Diff line
@@ -19,18 +19,19 @@ Optional properties: 
  the default 100 kHz frequency will be used.

  the default 100 kHz frequency will be used.

  For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are

  For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are

  100000 and 400000.

  100000 and 400000.

  For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,

  For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode

  possible values are 100000, 400000 and 1000000.

  Plus are supported, possible values are 100000, 400000 and 1000000.

- i2c-scl-rising-time-ns: Only for STM32F7, I2C SCL Rising time for the board

- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)

  (default: 25)

  For STM32F7, STM32H7 and STM32MP1 only.

- i2c-scl-falling-time-ns: Only for STM32F7, I2C SCL Falling time for the board

- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)

  (default: 10)

  For STM32F7, STM32H7 and STM32MP1 only.

  I2C Timings are derived from these 2 values

  I2C Timings are derived from these 2 values

- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG

- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode

  whether Fast Mode Plus speed is selected by slave.

  Plus speed is selected by slave.

	1st cell: phandle to syscfg

	1st cell: phandle to syscfg

	2nd cell: register offset within SYSCFG

	2nd cell: register offset within SYSCFG

	3rd cell: register bitmask for FMP bit

	3rd cell: register bitmask for FMP bit

  For STM32F7, STM32H7 and STM32MP1 only.





Example:

Example: