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Commit 36b8f204 authored by Manikandan Mohan's avatar Manikandan Mohan
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ARM: dts: msm: Add CNSS Bus Bandwidth voting data 

Update CNSS device tree node for interconnect settings and config
data for WLAN Bus bandwidth voting requirements.

Change-Id: I1071158c3f2b8da7d6b39b625e888a1a9b53a5fd
parent fa035180

bindings/cnss/cnss-wlan.txt

+3 −1
Original line number Diff line number Diff line
@@ -70,7 +70,9 @@ Optional properties: 
  - qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip

                       specifications, should be drived depending on products

  - qcom,wlan-cbc-enabled: boolean property to control cold boot calibration



  - interconnects: Interconnect framework setup for bus configuration

  - qcom,bus-bw-cfg-num: Number of bus bandwidth voting cases

  - qcom,bus-bw-cfg: Bus bandwidth voting data



Example:

qcom/lahaina.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -5254,6 +5254,24 @@ 
		wlan-ant-switch-supply = <&L7E>;

		qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;



		interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

		qcom,bus-bw-cfg-num = <7>;

		qcom,bus-bw-cfg =

		/* no vote */

		<0 0>,

		/* idle: 0-18 Mbps ddr freq: 451.2 MHz */

		<2250 1600000>,

		/* low: 18-60 Mbps ddr freq: 451.2 MHz */

		<7500 1600000>,

		/* medium: 60-240 Mbps ddr freq: 451.2 MHz */

		<30000 1804800>,

		/* high: 240 - 1080 Mbps ddr freq: 451.2 MHz */

		<100000 1804800>,

		/* high: 1080 - 1400 Mbps ddr freq: 451.2 MHz */

		<175000 1804800>,

		/* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */

		<7500 2188800>;



		mhi,max-channels = <30>;

		mhi,timeout = <10000>;

		mhi,buffer-len = <0x8000>;