Merge tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of...

Renesas Bus State Controller (BSC)

==================================

The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus

Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.

It provides an external bus for connecting multiple external devices to the

SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.

While the BSC is a fairly simple memory-mapped bus, it may be part of a PM

domain, and may have a gateable functional clock.

Before a device connected to the BSC can be accessed, the PM domain

containing the BSC must be powered on, and the functional clock

driving the BSC must be enabled.

The bindings for the BSC extend the bindings for "simple-pm-bus".

Required properties

  - compatible: Must contain an SoC-specific value, and "renesas,bsc" and

		"simple-pm-bus" as fallbacks.

                SoC-specific values can be:

		"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)

		"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)

  - #address-cells, #size-cells, ranges: Must describe the mapping between

		parent address and child address spaces.

  - reg: Must contain the base address and length to access the bus controller.

Optional properties:

  - interrupts: Must contain a reference to the BSC interrupt, if available.

  - clocks: Must contain a reference to the functional clock, if available.

  - power-domains: Must contain a reference to the PM domain, if available.

Example:

	bsc: bus@fec10000 {

		compatible = "renesas,bsc-sh73a0", "renesas,bsc",

			     "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x20000000>;

		reg = <0xfec10000 0x400>;

		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&zb_clk>;

		power-domains = <&pd_a4s>;

	};

Simple Power-Managed Bus

========================

A Simple Power-Managed Bus is a transparent bus that doesn't need a real

driver, as it's typically initialized by the boot loader.

However, its bus controller is part of a PM domain, or under the control of a

functional clock.  Hence, the bus controller's PM domain and/or clock must be

enabled for child devices connected to the bus (either on-SoC or externally)

to function.

While "simple-pm-bus" follows the "simple-bus" set of properties, as specified

in ePAPR, it is not an extension of "simple-bus".

Required properties:

  - compatible: Must contain at least "simple-pm-bus".

		Must not contain "simple-bus".

		It's recommended to let this be preceded by one or more

		vendor-specific compatible values.

  - #address-cells, #size-cells, ranges: Must describe the mapping between

		parent address and child address spaces.

Optional platform-specific properties for clock or PM domain control (at least

one of them is required):

  - clocks: Must contain a reference to the functional clock(s),

  - power-domains: Must contain a reference to the PM domain.

Please refer to the binding documentation for the clock and/or PM domain

providers for more details.

Example:

	bsc: bus@fec10000 {

		compatible = "renesas,bsc-sh73a0", "renesas,bsc",

			     "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x20000000>;

		reg = <0xfec10000 0x400>;

		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&zb_clk>;

		power-domains = <&pd_a4s>;

	};

* Renesas R8A7778 Clock Pulse Generator (CPG)

The CPG generates core clocks for the R8A7778. It includes two PLLs and

several fixed ratio dividers

Required Properties:

  - compatible: Must be "renesas,r8a7778-cpg-clocks"

  - reg: Base address and length of the memory resource used by the CPG

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are

    "plla", "pllb", "b", "out", "p", "s", and "s1".

Example

-------

	cpg_clocks: cpg_clocks@ffc80000 {

		compatible = "renesas,r8a7778-cpg-clocks";

		reg = <0xffc80000 0x80>;

		#clock-cells = <1>;

		clocks = <&extal_clk>;

		clock-output-names = "plla", "pllb", "b",

				     "out", "p", "s", "s1";

	};

nxp,pca9557		8-bit I2C-bus and SMBus I/O port with reset

nxp,pcf8563		Real-time clock/calendar

nxp,pcf85063		Tiny Real-Time Clock

oki,ml86v7667		OKI ML86V7667 video decoder

ovti,ov5642		OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus

pericom,pt7c4338	Real-time Clock Module

plx,pex8648		48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch

	r7s72100-genmai.dtb \

	r8a73a4-ape6evm.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen.dtb \

	r8a7790-lager.dtb \

	r8a7791-henninger.dtb \