Loading qcom/monaco-rumi.dtsi +0 −10 Original line number Diff line number Diff line #include <dt-bindings/clock/qcom,gcc-monaco.h> &soc { timer { clock-frequency = <5000000>; Loading @@ -15,12 +13,4 @@ }; &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; #include "monaco-stub-regulator.dtsi" qcom/monaco.dtsi +1 −18 Original line number Diff line number Diff line Loading @@ -677,25 +677,8 @@ }; }; bi_tcxo: bi_tcxo { compatible = "fixed-factor-clock"; clock-mult = <1>; clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; bi_tcxo_ao: bi_tcxo_ao { compatible = "fixed-factor-clock"; clock-mult = <1>; clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; rpmcc: qcom,rpmcc { compatible = "qcom,dummycc"; clock-output-names = "rpmcc_clocks"; compatible = "qcom,rpmcc-monaco"; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/monaco-rumi.dtsi +0 −10 Original line number Diff line number Diff line #include <dt-bindings/clock/qcom,gcc-monaco.h> &soc { timer { clock-frequency = <5000000>; Loading @@ -15,12 +13,4 @@ }; &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; #include "monaco-stub-regulator.dtsi"
qcom/monaco.dtsi +1 −18 Original line number Diff line number Diff line Loading @@ -677,25 +677,8 @@ }; }; bi_tcxo: bi_tcxo { compatible = "fixed-factor-clock"; clock-mult = <1>; clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; bi_tcxo_ao: bi_tcxo_ao { compatible = "fixed-factor-clock"; clock-mult = <1>; clock-div = <2>; clocks = <&xo_board>; #clock-cells = <0>; }; rpmcc: qcom,rpmcc { compatible = "qcom,dummycc"; clock-output-names = "rpmcc_clocks"; compatible = "qcom,rpmcc-monaco"; #clock-cells = <1>; #reset-cells = <1>; }; Loading