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Commit 36637cf1 authored by Sajini R's avatar Sajini R Committed by Madan Koyyalamudi
Browse files

fw-api: Add ipq5332 target header files to fw-api project

Added ipq5332 target header files under qca5332 to make fw-api
project compatible to host.

Change-Id: Iee6b3f2a809f31e62b45a0f6e9a7cbb66e070fa0
parent 03db641d
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hw/qca5332/HALcomdef.h

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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H

/*
 * Assembly wrapper
 */
#ifndef _ARM_ASM_

/*
 * C++ wrapper
 */
#ifdef __cplusplus
extern "C" {
#endif

#include "com_dtypes.h"

/* -----------------------------------------------------------------------
** Types
** ----------------------------------------------------------------------- */

/*
 * Standard integer types.
 *
 * bool32  - boolean, 32 bit (TRUE or FALSE)
 */
#ifndef _BOOL32_DEFINED
typedef  unsigned long int  bool32;
#define _BOOL32_DEFINED
#endif

/*
 * Macro to allow forcing an enum to 32 bits.  The argument should be
 * an identifier in the namespace of the enumeration in question, i.e.
 * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
 */
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF

/*===========================================================================

FUNCTION inp, outp, inpw, outpw, inpdw, outpdw

DESCRIPTION
  IN/OUT port macros for byte and word ports, typically inlined by compilers
  which support these routines

PARAMETERS
  inp(   xx_addr )
  inpw(  xx_addr )
  inpdw( xx_addr )
  outp(   xx_addr, xx_byte_val  )
  outpw(  xx_addr, xx_word_val  )
  outpdw( xx_addr, xx_dword_val )
      xx_addr      - Address of port to read or write (may be memory mapped)
      xx_byte_val  - 8 bit value to write
      xx_word_val  - 16 bit value to write
      xx_dword_val - 32 bit value to write

DEPENDENCIES
  None

RETURN VALUE
  inp/inpw/inpdw: the byte, word or dword read from the given address
  outp/outpw/outpdw: the byte, word or dword written to the given address

SIDE EFFECTS
  None.

===========================================================================*/

  /* ARM based targets use memory mapped i/o, so the inp/outp calls are
  ** macroized to access memory directly
  */

  #define inp(port)         (*((volatile byte *) (port)))
  #define inpw(port)        (*((volatile word *) (port)))
  #define inpdw(port)       (*((volatile dword *)(port)))

  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))

#ifdef __cplusplus
}
#endif

#endif /* !_ARM_ASM_ */

#endif /* HAL_COMDEF_H */

hw/qca5332/HALhwio.h

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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

 
 
 
 
 
 
 


#ifndef _ACK_REPORT_H_
#define _ACK_REPORT_H_
#if !defined(__ASSEMBLER__)
#endif

#define NUM_OF_DWORDS_ACK_REPORT 1


struct ack_report {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
             uint32_t selfgen_response_reason                                 :  4, // [3:0]
                      ax_trigger_type                                         :  4, // [7:4]
                      sr_ppdu                                                 :  1, // [8:8]
                      reserved                                                :  7, // [15:9]
                      frame_control                                           : 16; // [31:16]
#else
             uint32_t frame_control                                           : 16, // [31:16]
                      reserved                                                :  7, // [15:9]
                      sr_ppdu                                                 :  1, // [8:8]
                      ax_trigger_type                                         :  4, // [7:4]
                      selfgen_response_reason                                 :  4; // [3:0]
#endif
};


/* Description		SELFGEN_RESPONSE_REASON

			Field that indicates why the received frame needs a response
			 in SIFS time. The possible responses are listed in order.
			
			
			<enum 0     CTS_frame> 
			<enum 1     ACK_frame> 
			<enum 2     BA_frame > 
			<enum 3     Qboost_trigger> Qboost trigger received
			<enum 4     PSPOLL_trigger> PSPOLL trigger received
			<enum 5     UAPSD_trigger > Unscheduled APSD  trigger received
			 
			<enum 6     CBF_frame> the CBF frame needs to be send as
			 a result of NDP or BRPOLL
			<enum 7     ax_su_trigger> 11ax trigger received for this
			 device
			<enum 8     ax_wildcard_trigger> 11ax wildcardtrigger has
			 been received 
			<enum 9     ax_unassoc_wildcard_trigger> 11ax wildcard trigger
			 for unassociated STAs has been received
			<enum 12     eht_su_trigger> EHT R1 trigger received for
			 this device
			
			<enum 10     MU_UL_response_to_response>
			
			<enum 11     Ranging_NDP_LMR_frames> Ranging NDP + LMR need
			 to be sent in response to ranging NDPA + NDP
			
			<legal 0-12>
*/

#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f


/* Description		AX_TRIGGER_TYPE

			Field Only valid when selfgen_response_reason is an 11ax
			 related trigger
			
			The 11AX trigger type/ trigger number:
			It identifies which trigger was received.
			<enum 0 ax_trigger_basic>
			<enum 1 ax_trigger_brpoll>
			<enum 2 ax_trigger_mu_bar>
			<enum 3 ax_trigger_mu_rts>
			<enum 4 ax_trigger_buffer_size>
			<enum 5 ax_trigger_gcr_mu_bar>
			<enum 6 ax_trigger_BQRP> 
			<enum 7 ax_trigger_NDP_fb_report_poll> 
			<enum 8 ax_tb_ranging_trigger>
			<enum 9 ax_trigger_reserved_9>
			<enum 10 ax_trigger_reserved_10>
			<enum 11 ax_trigger_reserved_11>
			<enum 12 ax_trigger_reserved_12>
			<enum 13 ax_trigger_reserved_13>
			<enum 14 ax_trigger_reserved_14>
			<enum 15 ax_trigger_reserved_15>
			
			<legal all>
*/

#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0


/* Description		SR_PPDU

			Field only valid with SRP Responder support (not PoR in 
			Moselle/Maple/Spruce)
			
			Indicates if the received frame was sent using SRP as indicated
			 by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control' 
			in one of the MPDUs received
			<legal all>
*/

#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
#define ACK_REPORT_SR_PPDU_LSB                                                      8
#define ACK_REPORT_SR_PPDU_MSB                                                      8
#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100


/* Description		RESERVED

			<legal 0>
*/

#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
#define ACK_REPORT_RESERVED_LSB                                                     9
#define ACK_REPORT_RESERVED_MSB                                                     15
#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00


/* Description		FRAME_CONTROL

			Field not valid when selfgen_response_reason is MU_UL_response_to_response
			
			
			For SU receptions:
			frame control field of the received frame
			
			In 11ah Mode of Operation, for non-NDP frames the BW information
			 is extracted from Frame Control fields [11:8].
			
			Decode is as follows 
			
			Bits[11] - Dynamic/Static 
			Bits[10:8] - Channel BW
*/

#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000



#endif   // ACK_REPORT
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

 
 
 
 
 
 
 


#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif

#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2


struct buffer_addr_info {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
             uint32_t buffer_addr_31_0                                        : 32; // [31:0]
             uint32_t buffer_addr_39_32                                       :  8, // [7:0]
                      return_buffer_manager                                   :  4, // [11:8]
                      sw_buffer_cookie                                        : 20; // [31:12]
#else
             uint32_t buffer_addr_31_0                                        : 32; // [31:0]
             uint32_t sw_buffer_cookie                                        : 20, // [31:12]
                      return_buffer_manager                                   :  4, // [11:8]
                      buffer_addr_39_32                                       :  8; // [7:0]
#endif
};


/* Description		BUFFER_ADDR_31_0

			Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
			 descriptor OR Link Descriptor
			
			In case of 'NULL' pointer, this field is set to 0
			<legal all>
*/

#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                                    0x00000000
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB                                       0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB                                       31
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK                                      0xffffffff


/* Description		BUFFER_ADDR_39_32

			Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
			 descriptor OR Link Descriptor
			
			In case of 'NULL' pointer, this field is set to 0
			<legal all>
*/

#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                                   0x00000004
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB                                      0
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB                                      7
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK                                     0x000000ff


/* Description		RETURN_BUFFER_MANAGER

			Consumer: WBM
			Producer: SW/FW
			
			In case of 'NULL' pointer, this field is set to 0
			
			Indicates to which buffer manager the buffer OR MSDU_EXTENSION
			 descriptor OR link descriptor that is being pointed to 
			shall be returned after the frame has been processed. It
			 is used by WBM for routing purposes.
			
			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
			 to the WMB buffer idle list
			<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
			 to the WBM idle link descriptor idle list, where the chip
			 0 WBM is chosen in case of a multi-chip config
			<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
			 to the chip 1 WBM idle link descriptor idle list
			<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
			 to the chip 2 WBM idle link descriptor idle list
			<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 
			returned to chip 3 WBM idle link descriptor idle list
			<enum 4 FW_BM> This buffer shall be returned to the FW
			<enum 5 SW0_BM> This buffer shall be returned to the SW, 
			ring 0
			<enum 6 SW1_BM> This buffer shall be returned to the SW, 
			ring 1
			<enum 7 SW2_BM> This buffer shall be returned to the SW, 
			ring 2
			<enum 8 SW3_BM> This buffer shall be returned to the SW, 
			ring 3
			<enum 9 SW4_BM> This buffer shall be returned to the SW, 
			ring 4
			<enum 10 SW5_BM> This buffer shall be returned to the SW, 
			ring 5
			<enum 11 SW6_BM> This buffer shall be returned to the SW, 
			ring 6
			
			<legal 0-12>
*/

#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                               0x00000004
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                                  8
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                                  11
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                                 0x00000f00


/* Description		SW_BUFFER_COOKIE

			Cookie field exclusively used by SW. 
			
			In case of 'NULL' pointer, this field is set to 0
			
			HW ignores the contents, accept that it passes the programmed
			 value on to other descriptors together with the physical
			 address 
			
			Field can be used by SW to for example associate the buffers
			 physical address with the virtual address
			The bit definitions as used by SW are within SW HLD specification
			
			
			NOTE1:
			The three most significant bits can have a special meaning
			 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 
			and field transmit_bw_restriction is set
			
			In case of NON punctured transmission:
			Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
			Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
			Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
			Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
			Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
			Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
			Sw_buffer_cookie[19:18] = 2'b11: reserved
			
			In case of punctured transmission:
			Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
			Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
			Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
			Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
			Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
			Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
			Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
			Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
			Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
			Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
			Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
			Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
			Sw_buffer_cookie[19:18] = 2'b11: reserved
			
			Note: a punctured transmission is indicated by the presence
			 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
			
			<legal all>
*/

#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                                    0x00000004
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB                                       12
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB                                       31
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK                                      0xfffff000



#endif   // BUFFER_ADDR_INFO
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