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Commit 3657432a authored by Stefan Agner's avatar Stefan Agner Committed by Greg Kroah-Hartman
Browse files

ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand 

commit 9f1984c6ae30e2a379751339ce3375a21099b5d4 upstream

LLVM's integrated assembler does not accept r15 as mrc operand.
  arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv
  1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
                 ^

Use APSR_nzcv instead of r15. The GNU assembler supports this
syntax since binutils 2.21 [0].

[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076



Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 02c200fd

arch/arm/boot/compressed/head.S

+1 −1
Original line number Diff line number Diff line
@@ -1274,7 +1274,7 @@ iflush: 
__armv5tej_mmu_cache_flush:

		tst	r4, #1

		movne	pc, lr

1:		mrc	p15, 0, r15, c7, c14, 3	@ test,clean,invalidate D cache

1:		mrc	p15, 0, APSR_nzcv, c7, c14, 3	@ test,clean,invalidate D cache

		bne	1b

		mcr	p15, 0, r0, c7, c5, 0	@ flush I cache

		mcr	p15, 0, r0, c7, c10, 4	@ drain WB

arch/arm/mm/proc-arm1026.S

+2 −2
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all) 
	mov	ip, #0

__flush_whole_cache:

#ifndef CONFIG_CPU_DCACHE_DISABLE

1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate

1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate

	bne	1b

#endif

	tst	r2, #VM_EXEC
@@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm) 
#ifdef CONFIG_MMU

	mov	r1, #0

#ifndef CONFIG_CPU_DCACHE_DISABLE

1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate

1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate

	bne	1b

#endif

#ifndef CONFIG_CPU_ICACHE_DISABLE

arch/arm/mm/proc-arm926.S

+2 −2
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ __flush_whole_cache: 
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache

#else

1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate

1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate

	bne	1b

#endif

	tst	r2, #VM_EXEC
@@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm) 
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache

#else

@ && 'Clean & Invalidate whole DCache'

1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate

1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate

	bne	1b

#endif

	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache