Loading drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h +2 −1 Original line number Original line Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */ /* /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ */ #ifndef _CAM_IFE_CSID_175_200_H_ #ifndef _CAM_IFE_CSID_175_200_H_ Loading Loading @@ -47,6 +47,7 @@ static struct cam_ife_csid_pxl_reg_offset /* configurations */ /* configurations */ .pix_store_en_shift_val = 7, .pix_store_en_shift_val = 7, .early_eof_en_shift_val = 29, .early_eof_en_shift_val = 29, .horizontal_bin_en_shift_val = 2, .quad_cfa_bin_en_shift_val = 30, .quad_cfa_bin_en_shift_val = 30, .ccif_violation_en = 1, .ccif_violation_en = 1, }; }; Loading drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +3 −1 Original line number Original line Diff line number Diff line Loading @@ -2055,8 +2055,10 @@ static int cam_ife_csid_init_config_pxl_path( } } if (is_ipp && csid_hw->binning_supported && if (is_ipp && csid_hw->binning_supported && csid_hw->binning_enable) csid_hw->binning_enable) { val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); val |= (1 << pxl_reg->horizontal_bin_en_shift_val); } val |= (1 << pxl_reg->pix_store_en_shift_val); val |= (1 << pxl_reg->pix_store_en_shift_val); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + Loading Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h +2 −1 Original line number Original line Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */ /* /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ */ #ifndef _CAM_IFE_CSID_175_200_H_ #ifndef _CAM_IFE_CSID_175_200_H_ Loading Loading @@ -47,6 +47,7 @@ static struct cam_ife_csid_pxl_reg_offset /* configurations */ /* configurations */ .pix_store_en_shift_val = 7, .pix_store_en_shift_val = 7, .early_eof_en_shift_val = 29, .early_eof_en_shift_val = 29, .horizontal_bin_en_shift_val = 2, .quad_cfa_bin_en_shift_val = 30, .quad_cfa_bin_en_shift_val = 30, .ccif_violation_en = 1, .ccif_violation_en = 1, }; }; Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +3 −1 Original line number Original line Diff line number Diff line Loading @@ -2055,8 +2055,10 @@ static int cam_ife_csid_init_config_pxl_path( } } if (is_ipp && csid_hw->binning_supported && if (is_ipp && csid_hw->binning_supported && csid_hw->binning_enable) csid_hw->binning_enable) { val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); val |= (1 << pxl_reg->horizontal_bin_en_shift_val); } val |= (1 << pxl_reg->pix_store_en_shift_val); val |= (1 << pxl_reg->pix_store_en_shift_val); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + Loading