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Commit 35c37ade authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/icl: Define TA_TIMING_PARAM registers 



This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.

v2: Changes (Jani N)
    - Define mask/shift for bitfields
    - Use bitfields name as per BSPEC
    - Define remaining bitfields

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-8-git-send-email-madhav.chauhan@intel.com
parent 33868a91

drivers/gpu/drm/i915/i915_reg.h

+23 −0
Original line number Diff line number Diff line
@@ -10344,6 +10344,29 @@ enum skl_power_gate { 
#define  HS_EXIT_MASK			(0x7 << 0)

#define  HS_EXIT_SHIFT			0



#define _DPHY_TA_TIMING_PARAM_0		0x162188

#define _DPHY_TA_TIMING_PARAM_1		0x6c188

#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\

						   _DPHY_TA_TIMING_PARAM_0,\

						   _DPHY_TA_TIMING_PARAM_1)

#define _DSI_TA_TIMING_PARAM_0		0x6b098

#define _DSI_TA_TIMING_PARAM_1		0x6b898

#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\

						   _DSI_TA_TIMING_PARAM_0,\

						   _DSI_TA_TIMING_PARAM_1)

#define  TA_SURE_OVERRIDE		(1 << 31)

#define  TA_SURE(x)			((x) << 16)

#define  TA_SURE_MASK			(0x1f << 16)

#define  TA_SURE_SHIFT			16

#define  TA_GO_OVERRIDE		(1 << 15)

#define  TA_GO(x)			((x) << 8)

#define  TA_GO_MASK			(0xf << 8)

#define  TA_GO_SHIFT			8

#define  TA_GET_OVERRIDE		(1 << 7)

#define  TA_GET(x)			((x) << 0)

#define  TA_GET_MASK			(0xf << 0)

#define  TA_GET_SHIFT			0



/* bits 31:0 */

#define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)

#define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)