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Commit 35b876db authored by Anusha Srivatsa's avatar Anusha Srivatsa Committed by Manasi Navare
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drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming 



Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.

Credits to Manasi for noticing bSpec change.

Suggested-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-1-manasi.d.navare@intel.com
parent 5a4712f4

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -10977,6 +10977,7 @@ enum skl_power_gate { 
#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \

							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \

							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)

#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)

#define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)

#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)