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Commit 35ab4fd2 authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by Chris Wilson
Browse files

drm/i915/perf: reuse intel_lrc ctx regs macro 



Abstract the context image access a bit.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180813080218.28994-3-tvrtko.ursulin@linux.intel.com
parent 1c71bc56

drivers/gpu/drm/i915/i915_perf.c

+16 −18
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ 
#include "i915_oa_cflgt3.h"

#include "i915_oa_cnl.h"

#include "i915_oa_icl.h"

#include "intel_lrc_reg.h"



/* HW requires this to be a power of two, between 128k and 16M, though driver

 * is currently generally designed assuming the largest 16M size is used such
@@ -1636,27 +1637,25 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, 
	u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;

	u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;

	/* The MMIO offsets for Flex EU registers aren't contiguous */

	u32 flex_mmio[] = {

		i915_mmio_reg_offset(EU_PERF_CNTL0),

		i915_mmio_reg_offset(EU_PERF_CNTL1),

		i915_mmio_reg_offset(EU_PERF_CNTL2),

		i915_mmio_reg_offset(EU_PERF_CNTL3),

		i915_mmio_reg_offset(EU_PERF_CNTL4),

		i915_mmio_reg_offset(EU_PERF_CNTL5),

		i915_mmio_reg_offset(EU_PERF_CNTL6),

	i915_reg_t flex_regs[] = {

		EU_PERF_CNTL0,

		EU_PERF_CNTL1,

		EU_PERF_CNTL2,

		EU_PERF_CNTL3,

		EU_PERF_CNTL4,

		EU_PERF_CNTL5,

		EU_PERF_CNTL6,

	};

	int i;



	reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL);

	reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent <<

				      GEN8_OA_TIMER_PERIOD_SHIFT) |

				     (dev_priv->perf.oa.periodic ?

				      GEN8_OA_TIMER_ENABLE : 0) |

				     GEN8_OA_COUNTER_RESUME;

	CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,

		(dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |

		(dev_priv->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |

		GEN8_OA_COUNTER_RESUME);



	for (i = 0; i < ARRAY_SIZE(flex_mmio); i++) {

	for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {

		u32 state_offset = ctx_flexeu0 + i * 2;

		u32 mmio = flex_mmio[i];

		u32 mmio = i915_mmio_reg_offset(flex_regs[i]);



		/*

		 * This arbitrary default will select the 'EU FPU0 Pipeline
@@ -1676,8 +1675,7 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, 
			}

		}



		reg_state[state_offset] = mmio;

		reg_state[state_offset+1] = value;

		CTX_REG(reg_state, state_offset, flex_regs[i], value);

	}

}