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Commit 353e99f5 authored by Urvashi Agrawal's avatar Urvashi Agrawal
Browse files

msm: kgsl: Initialize LPAC registers 



Some LPAC registers need to be initialized during boot
to avoid any LPAC side glitches at the time when GC is
processing SET_SECURE packets.

Change-Id: Id5ace195cb2e42fdd1661b04a40d3385cbce5635
Signed-off-by: default avatarUrvashi Agrawal <urvaagra@codeaurora.org>
parent b7f099b1

drivers/gpu/msm/a6xx_reg.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -118,6 +118,11 @@ 
#define A6XX_CP_APERTURE_CNTL_CD         0xA03

#define A6XX_CP_APERTURE_CNTL_CD         0xA03

#define A6XX_VSC_ADDR_MODE_CNTL          0xC01

#define A6XX_VSC_ADDR_MODE_CNTL          0xC01





/* LPAC registers */

#define A6XX_CP_LPAC_ROQ_THRESHOLDS_1    0xB32

#define A6XX_CP_LPAC_ROQ_THRESHOLDS_2    0xB33

#define A6XX_CP_LPAC_PROG_FIFO_SIZE      0xB34



/* RBBM registers */

/* RBBM registers */

#define A6XX_RBBM_INT_0_STATUS                   0x201

#define A6XX_RBBM_INT_0_STATUS                   0x201

#define A6XX_RBBM_STATUS                         0x210

#define A6XX_RBBM_STATUS                         0x210

drivers/gpu/msm/adreno_a6xx.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -445,6 +445,14 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	}

	}





	if (adreno_is_a660(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_2,

						0x00800060);

		kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_1,

						0x40202016);

		kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000080);

	}



	if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

	if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

		/* For A612 and A610 Mem pool size is reduced to 48 */

		/* For A612 and A610 Mem pool size is reduced to 48 */

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48);