Loading qcom/lahaina-pcie.dtsi +1 −5 Original line number Diff line number Diff line Loading @@ -101,6 +101,7 @@ qcom,boot-option = <0x1>; qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <10000>; qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; Loading @@ -109,11 +110,6 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; qcom,phy-core-pll-en-mux = <7>; qcom,phy-c-ready-status = <0x178>; qcom,pcie-phy-ver = <10099>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; Loading Loading
qcom/lahaina-pcie.dtsi +1 −5 Original line number Diff line number Diff line Loading @@ -101,6 +101,7 @@ qcom,boot-option = <0x1>; qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <10000>; qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; Loading @@ -109,11 +110,6 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; qcom,phy-core-pll-en-mux = <7>; qcom,phy-c-ready-status = <0x178>; qcom,pcie-phy-ver = <10099>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; Loading