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Commit 35051f84 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'samsung-dt-5.3-3' of... 

Merge tag 'samsung-dt-5.3-3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM changes for v5.3, third round

1. Fix imprecise abort on Exynos4210 caused by newly added Mali nodes,
2. Reorganize Mali nodes under /soc,
3. Adjust buck regulators voltages on Arndale Octa and Odroid XU3/XU4
   family to sane values.

* tag 'samsung-dt-5.3-3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa
  ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family
  ARM: dts: exynos: Move Mali400 GPU node to "/soc"
  ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210

Link: https://lore.kernel.org/r/20190707180115.5562-1-krzk@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4471e44f 841ed602

arch/arm/boot/dts/exynos3250.dtsi

+33 −33
Original line number Diff line number Diff line
@@ -126,39 +126,6 @@ 
		};

	};



	gpu: gpu@13000000 {

		compatible = "samsung,exynos4210-mali", "arm,mali-400";

		reg = <0x13000000 0x10000>;

		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp",

				  "gpmmu",

				  "pp0",

				  "ppmmu0",

				  "pp1",

				  "ppmmu1",

				  "pp2",

				  "ppmmu2",

				  "pp3",

				  "ppmmu3",

				  "pmu";

		clocks = <&cmu CLK_G3D>,

			 <&cmu CLK_SCLK_G3D>;

		clock-names = "bus", "core";

		power-domains = <&pd_g3d>;

		status = "disabled";

		/* TODO: operating points for DVFS, assigned clock as 134 MHz */

	};



	pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -495,6 +462,39 @@ 
			status = "disabled";

		};



		gpu: gpu@13000000 {

			compatible = "samsung,exynos4210-mali", "arm,mali-400";

			reg = <0x13000000 0x10000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp",

					  "gpmmu",

					  "pp0",

					  "ppmmu0",

					  "pp1",

					  "ppmmu1",

					  "pp2",

					  "ppmmu2",

					  "pp3",

					  "ppmmu3",

					  "pmu";

			clocks = <&cmu CLK_G3D>,

				 <&cmu CLK_SCLK_G3D>;

			clock-names = "bus", "core";

			power-domains = <&pd_g3d>;

			status = "disabled";

			/* TODO: operating points for DVFS, assigned clock as 134 MHz */

		};



		mfc: codec@13400000 {

			compatible = "samsung,mfc-v7";

			reg = <0x13400000 0x10000>;

arch/arm/boot/dts/exynos4.dtsi

+14 −36
Original line number Diff line number Diff line
@@ -51,42 +51,6 @@ 
		serial3 = &serial_3;

	};



	gpu: gpu@13000000 {

		compatible = "samsung,exynos4210-mali", "arm,mali-400";

		reg = <0x13000000 0x10000>;

		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp",

				  "gpmmu",

				  "pp0",

				  "ppmmu0",

				  "pp1",

				  "ppmmu1",

				  "pp2",

				  "ppmmu2",

				  "pp3",

				  "ppmmu3",

				  "pmu";

		/*

		 * CLK_G3D is not actually bus clock but a IP-level clock.

		 * The bus clock is not described in hardware manual.

		 */

		clocks = <&clock CLK_G3D>,

			 <&clock CLK_SCLK_G3D>;

		clock-names = "bus", "core";

		power-domains = <&pd_g3d>;

		status = "disabled";

	};



	pmu: pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&combiner>;
@@ -451,6 +415,20 @@ 
			};

		};



		gpu: gpu@13000000 {

			compatible = "samsung,exynos4210-mali", "arm,mali-400";

			reg = <0x13000000 0x10000>;

			/*

			 * CLK_G3D is not actually bus clock but a IP-level clock.

			 * The bus clock is not described in hardware manual.

			 */

			clocks = <&clock CLK_G3D>,

				 <&clock CLK_SCLK_G3D>;

			clock-names = "bus", "core";

			power-domains = <&pd_g3d>;

			status = "disabled";

		};



		i2s1: i2s@13960000 {

			compatible = "samsung,s3c6410-i2s";

			reg = <0x13960000 0x100>;

arch/arm/boot/dts/exynos4210.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -450,6 +450,26 @@ 
};



&gpu {

	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "gp",

			  "gpmmu",

			  "pp0",

			  "ppmmu0",

			  "pp1",

			  "ppmmu1",

			  "pp2",

			  "ppmmu2",

			  "pp3",

			  "ppmmu3";

	operating-points-v2 = <&gpu_opp_table>;



	gpu_opp_table: opp_table {

arch/arm/boot/dts/exynos4412.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -717,6 +717,28 @@ 
};



&gpu {

	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "gp",

			  "gpmmu",

			  "pp0",

			  "ppmmu0",

			  "pp1",

			  "ppmmu1",

			  "pp2",

			  "ppmmu2",

			  "pp3",

			  "ppmmu3",

			  "pmu";

	operating-points-v2 = <&gpu_opp_table>;



	gpu_opp_table: opp_table {

arch/arm/boot/dts/exynos5420-arndale-octa.dts

+3 −3
Original line number Diff line number Diff line
@@ -723,15 +723,15 @@ 


			buck7_reg: BUCK7 {

				regulator-name = "VIN_LLDO_1V4";

				regulator-min-microvolt = <800000>;

				regulator-min-microvolt = <1200000>;

				regulator-max-microvolt = <1500000>;

				regulator-always-on;

			};



			buck8_reg: BUCK8 {

				regulator-name = "VIN_MLDO_2V0";

				regulator-min-microvolt = <800000>;

				regulator-max-microvolt = <2000000>;

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <2100000>;

				regulator-always-on;

			};