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Commit 3461cbfd authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

Merge tag 'topic/hdr-formats-2019-03-07' of... 

Merge tag 'topic/hdr-formats-2019-03-07' of git://anongit.freedesktop.org/drm/drm-misc

 into drm-intel-next-queued

Add support for Y21x and Y41x to drm core and i915, and P01x support to i915.

Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f2485309-d645-bed4-95f4-e66ff312aa05@linux.intel.com
parents bd2dba19 296e9b19

drivers/gpu/drm/drm_fourcc.c

+6 −0
Original line number Diff line number Diff line
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format) 
		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_XYUV8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },

		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

		{ .format = DRM_FORMAT_Y0L0,		.depth = 0,  .num_planes = 1,

		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },

		  .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },

drivers/gpu/drm/i915/i915_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -6602,13 +6602,22 @@ enum { 
#define   PLANE_CTL_FORMAT_YUV422		(0 << 24)

#define   PLANE_CTL_FORMAT_NV12			(1 << 24)

#define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)

#define   PLANE_CTL_FORMAT_P010			(3 << 24)

#define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)

#define   PLANE_CTL_FORMAT_P012			(5 << 24)

#define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)

#define   PLANE_CTL_FORMAT_P016			(7 << 24)

#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)

#define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)

#define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)

#define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)

#define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */

#define   PLANE_CTL_FORMAT_Y210                 (1 << 23)

#define   PLANE_CTL_FORMAT_Y212                 (3 << 23)

#define   PLANE_CTL_FORMAT_Y216                 (5 << 23)

#define   PLANE_CTL_FORMAT_Y410                 (7 << 23)

#define   PLANE_CTL_FORMAT_Y412                 (9 << 23)

#define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)

#define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)

#define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)

#define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)

drivers/gpu/drm/i915/intel_atomic_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ 
		new_crtc_state->active_planes |= BIT(plane->id);



	if (new_plane_state->base.visible &&

	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)

	    is_planar_yuv_format(new_plane_state->base.fb->format->format))

		new_crtc_state->nv12_planes |= BIT(plane->id);



	if (new_plane_state->base.visible &&

drivers/gpu/drm/i915/intel_display.c

+51 −6
Original line number Diff line number Diff line
@@ -2644,6 +2644,24 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 
		return DRM_FORMAT_RGB565;

	case PLANE_CTL_FORMAT_NV12:

		return DRM_FORMAT_NV12;

	case PLANE_CTL_FORMAT_P010:

		return DRM_FORMAT_P010;

	case PLANE_CTL_FORMAT_P012:

		return DRM_FORMAT_P012;

	case PLANE_CTL_FORMAT_P016:

		return DRM_FORMAT_P016;

	case PLANE_CTL_FORMAT_Y210:

		return DRM_FORMAT_Y210;

	case PLANE_CTL_FORMAT_Y212:

		return DRM_FORMAT_Y212;

	case PLANE_CTL_FORMAT_Y216:

		return DRM_FORMAT_Y216;

	case PLANE_CTL_FORMAT_Y410:

		return DRM_FORMAT_Y410;

	case PLANE_CTL_FORMAT_Y412:

		return DRM_FORMAT_Y412;

	case PLANE_CTL_FORMAT_Y416:

		return DRM_FORMAT_Y416;

	default:

	case PLANE_CTL_FORMAT_XRGB_8888:

		if (rgb_order) {
@@ -3142,7 +3160,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) 
	 * Handle the AUX surface first since

	 * the main surface setup depends on it.

	 */

	if (fb->format->format == DRM_FORMAT_NV12) {

	if (is_planar_yuv_format(fb->format->format)) {

		ret = skl_check_nv12_aux_surface(plane_state);

		if (ret)

			return ret;
@@ -3567,6 +3585,24 @@ static u32 skl_plane_ctl_format(u32 pixel_format) 
		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;

	case DRM_FORMAT_NV12:

		return PLANE_CTL_FORMAT_NV12;

	case DRM_FORMAT_P010:

		return PLANE_CTL_FORMAT_P010;

	case DRM_FORMAT_P012:

		return PLANE_CTL_FORMAT_P012;

	case DRM_FORMAT_P016:

		return PLANE_CTL_FORMAT_P016;

	case DRM_FORMAT_Y210:

		return PLANE_CTL_FORMAT_Y210;

	case DRM_FORMAT_Y212:

		return PLANE_CTL_FORMAT_Y212;

	case DRM_FORMAT_Y216:

		return PLANE_CTL_FORMAT_Y216;

	case DRM_FORMAT_Y410:

		return PLANE_CTL_FORMAT_Y410;

	case DRM_FORMAT_Y412:

		return PLANE_CTL_FORMAT_Y412;

	case DRM_FORMAT_Y416:

		return PLANE_CTL_FORMAT_Y416;

	default:

		MISSING_CASE(pixel_format);

	}
@@ -4996,9 +5032,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 
		return 0;

	}



	if (format && format->format == DRM_FORMAT_NV12 &&

	if (format && is_planar_yuv_format(format->format) &&

	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {

		DRM_DEBUG_KMS("NV12: src dimensions not met\n");

		DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");

		return -EINVAL;

	}
@@ -5072,7 +5108,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 


	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */

	if (!icl_is_hdr_plane(intel_plane) &&

	    fb && fb->format->format == DRM_FORMAT_NV12)

	    fb && is_planar_yuv_format(fb->format->format))

		need_scaler = true;



	ret = skl_update_scaler(crtc_state, force_detach,
@@ -5109,6 +5145,15 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 
	case DRM_FORMAT_UYVY:

	case DRM_FORMAT_VYUY:

	case DRM_FORMAT_NV12:

	case DRM_FORMAT_P010:

	case DRM_FORMAT_P012:

	case DRM_FORMAT_P016:

	case DRM_FORMAT_Y210:

	case DRM_FORMAT_Y212:

	case DRM_FORMAT_Y216:

	case DRM_FORMAT_Y410:

	case DRM_FORMAT_Y412:

	case DRM_FORMAT_Y416:

		break;

	default:

		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -11173,7 +11218,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 
		}



		if (!linked_state) {

			DRM_DEBUG_KMS("Need %d free Y planes for NV12\n",

			DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",

				      hweight8(crtc_state->nv12_planes));



			return -EINVAL;
@@ -13893,7 +13938,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, 
	 *            or

	 *    cdclk/crtc_clock

	 */

	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;

	mult = is_planar_yuv_format(pixel_format) ? 2 : 3;

	tmpclk1 = (1 << 16) * mult - 1;

	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);

	max_scale = min(tmpclk1, tmpclk2);

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -2410,6 +2410,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, 




/* intel_sprite.c */

bool is_planar_yuv_format(u32 pixelformat);

int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,

			     int usecs);

struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,