Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 341102c3 authored by mike.travis@hpe.com's avatar mike.travis@hpe.com Committed by Thomas Gleixner
Browse files

x86/tsc: Add option that TSC on Socket 0 being non-zero is valid 



Add a flag to indicate and process that TSC counters are on chassis
that reset at different times during system startup.  Therefore which
TSC ADJUST values should be zero is not predictable.

Signed-off-by: default avatarMike Travis <mike.travis@hpe.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarDimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: default avatarRuss Anderson <russ.anderson@hpe.com>
Reviewed-by: default avatarAndrew Banman <andrew.abanman@hpe.com>
Reviewed-by: default avatarPeter Zijlstra <peterz@infradead.org>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163201.944370012@stormcage.americas.sgi.com
parent ccb64941

arch/x86/include/asm/tsc.h

+2 −0
Original line number Diff line number Diff line
@@ -36,11 +36,13 @@ extern void tsc_init(void); 
extern void mark_tsc_unstable(char *reason);

extern int unsynchronized_tsc(void);

extern int check_tsc_unstable(void);

extern void mark_tsc_async_resets(char *reason);

extern unsigned long native_calibrate_cpu(void);

extern unsigned long native_calibrate_tsc(void);

extern unsigned long long native_sched_clock_from_tsc(u64 tsc);



extern int tsc_clocksource_reliable;

extern bool tsc_async_resets;



/*

 * Boot-time check whether the TSCs are synchronized across

arch/x86/kernel/tsc_sync.c

+35 −4
Original line number Diff line number Diff line
@@ -30,6 +30,20 @@ struct tsc_adjust { 


static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);



/*

 * TSC's on different sockets may be reset asynchronously.

 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.

 */

bool __read_mostly tsc_async_resets;



void mark_tsc_async_resets(char *reason)

{

	if (tsc_async_resets)

		return;

	tsc_async_resets = true;

	pr_info("tsc: Marking TSC async resets true due to %s\n", reason);

}



void tsc_verify_tsc_adjust(bool resume)

{

	struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
@@ -71,12 +85,22 @@ static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval, 
	 * non zero. We don't do that on non boot cpus because physical

	 * hotplug should have set the ADJUST register to a value > 0 so

	 * the TSC is in sync with the already running cpus.

	 *

	 * Also don't force the ADJUST value to zero if that is a valid value

	 * for socket 0 as determined by the system arch.  This is required

	 * when multiple sockets are reset asynchronously with each other

	 * and socket 0 may not have an TSC ADJUST value of 0.

	 */

	if (bootcpu && bootval != 0) {

		pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,

			bootval);

		if (likely(!tsc_async_resets)) {

			pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",

				cpu, bootval);

			wrmsrl(MSR_IA32_TSC_ADJUST, 0);

			bootval = 0;

		} else {

			pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",

				cpu, bootval);

		}

	}

	cur->adjusted = bootval;

}
@@ -117,6 +141,13 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu) 
	cur->nextcheck = jiffies + HZ;

	cur->warned = false;



	/*

	 * If a non-zero TSC value for socket 0 may be valid then the default

	 * adjusted value cannot assumed to be zero either.

	 */

	if (tsc_async_resets)

		cur->adjusted = bootval;



	/*

	 * Check whether this CPU is the first in a package to come up. In

	 * this case do not check the boot value against another package