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Commit 340ffd26 authored by Valentine Barshak's avatar Valentine Barshak Committed by Josh Boyer
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[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround 



Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: default avatarValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
parent 8112753b

arch/powerpc/kernel/cpu_setup_44x.S

+24 −1
Original line number Diff line number Diff line
@@ -20,7 +20,14 @@ 
_GLOBAL(__setup_cpu_440ep)

	b	__init_fpu_44x

_GLOBAL(__setup_cpu_440epx)

	b	__init_fpu_44x

	mflr	r4

	bl	__init_fpu_44x

	bl	__plb_disable_wrp

	mtlr	r4

	blr

_GLOBAL(__setup_cpu_440grx)

	b	__plb_disable_wrp





/* enable APU between CPU and FPU */

_GLOBAL(__init_fpu_44x)
@@ -31,3 +38,19 @@ _GLOBAL(__init_fpu_44x) 
	isync

	blr



/*

 * Workaround for the incorrect write to DDR SDRAM errata.

 * The write address can be corrupted during writes to

 * DDR SDRAM when write pipelining is enabled on PLB0.

 * Disable write pipelining here.

 */

#define DCRN_PLB4A0_ACR	0x81



_GLOBAL(__plb_disable_wrp)

	mfdcr	r3,DCRN_PLB4A0_ACR

	/* clear WRP bit in PLB4A0_ACR */

	rlwinm	r3,r3,0,8,6

	mtdcr	DCRN_PLB4A0_ACR,r3

	isync

	blr

arch/powerpc/kernel/cputable.c

+3 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ EXPORT_SYMBOL(cur_cpu_spec); 
#ifdef CONFIG_PPC32

extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);

extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);

extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);

extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);

extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);

extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
@@ -1146,6 +1147,8 @@ static struct cpu_spec cpu_specs[] = { 
		.cpu_user_features	= COMMON_USER_BOOKE,

		.icache_bsize		= 32,

		.dcache_bsize		= 32,

		.cpu_setup		= __setup_cpu_440grx,

		.platform		= "ppc440",

	},

	{	/* 440GP Rev. B */

		.pvr_mask		= 0xf0000fff,