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Commit 3403df81 authored by Asutosh Das's avatar Asutosh Das
Browse files

scsi: ufs-qcom: Clock scaling code restructure 



Code restructuring of clock scaling and fixes.

Change-Id: Id11364832464f4419ec9a8daba8fb9e6b7ca6dca
Signed-off-by: default avatarAsutosh Das <asutoshd@codeaurora.org>
parent a27ae1c7

drivers/scsi/ufs/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ config SCSI_UFS_DWC_TC_PLATFORM 


config SCSI_UFS_QCOM

	tristate "QCOM specific hooks to UFS controller platform driver"

	depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM

	depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM && PHY_QCOM_UFS

	select RESET_CONTROLLER

	help

	  This selects the QCOM specific additions to UFSHCD platform driver.

drivers/scsi/ufs/ufs-qcom.c

+169 −34
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/gpio/consumer.h>

#include <linux/reset-controller.h>

#include <linux/interconnect.h>

#include <linux/phy/phy-qcom-ufs.h>



#include "ufshcd.h"

#include "ufshcd-pltfrm.h"
@@ -46,9 +47,11 @@ static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 
static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);

static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);

static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,

						       u32 clk_cycles);

						       u32 clk_1us_cycles,

						       u32 clk_40ns_cycles);

static void ufs_qcom_parse_gear_limits(struct ufs_qcom_host *host);

static void ufs_qcom_parse_lpm(struct ufs_qcom_host *host);

static int ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(struct ufs_hba *hba);



static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)

{
@@ -200,8 +203,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 
static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)

{

	u32 tx_lanes;

	int err = 0;

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	struct phy *phy = host->generic_phy;



	err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);

	if (err)

		goto out;



	return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);

	ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);

	/*

	 * Some UFS devices send incorrect LineCfg data as part of power mode

	 * change sequence which may cause host PHY to go into bad state.

	 * Disabling Rx LineCfg of host PHY should help avoid this.

	 */

	if (ufshcd_get_local_unipro_ver(hba) == UFS_UNIPRO_VER_1_41)

		ufs_qcom_phy_ctrl_rx_linecfg(phy, false);



out:

	return err;

}



static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
@@ -341,8 +361,9 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 
/**

 * Returns zero for success and non-zero in case of a failure

 */

static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,

			       u32 hs, u32 rate, bool update_link_startup_timer)

static int __ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,

			       u32 hs, u32 rate, bool update_link_startup_timer,

			       bool is_pre_scale_up)

{

	int ret = 0;

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -376,9 +397,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 
	 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &

	 * UFS_REG_PA_LINK_STARTUP_TIMER

	 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt

	 * Aggregation logic.

	 * Aggregation logic / Auto hibern8 logic.

	 * It is mandatory to write SYS1CLK_1US_REG register on UFS host

	 * controller V4.0.0 onwards.

	*/

	if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))

	if (ufs_qcom_cap_qunipro(host) &&

	    (!(ufshcd_is_intr_aggr_allowed(hba) ||

	       host->hw_ver.major >= 4)))

		goto out;



	if (gear == 0) {
@@ -387,9 +412,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 
	}



	list_for_each_entry(clki, &hba->clk_list_head, list) {

		if (!strcmp(clki->name, "core_clk"))

		if (!strcmp(clki->name, "core_clk")) {

			if (is_pre_scale_up)

				core_clk_rate = clki->max_freq;

			else

				core_clk_rate = clk_get_rate(clki->clk);

		}

	}



	/* If frequency is smaller than 1MHz, set to 1MHz */

	if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
@@ -485,11 +514,19 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 
	return ret;

}



static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,

			       u32 hs, u32 rate, bool update_link_startup_timer)

{

	return  __ufs_qcom_cfg_timers(hba, gear, hs, rate,

				      update_link_startup_timer, false);

}



static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,

					enum ufs_notify_change_status status)

{

	int err = 0;

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	struct phy *phy = host->generic_phy;



	switch (status) {

	case PRE_CHANGE:
@@ -501,14 +538,14 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 
			goto out;

		}



		if (ufs_qcom_cap_qunipro(host))

			/*

			 * set unipro core clock cycles to 150 & clear clock

			 * divider

			 */

			err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,

									  150);

		ufs_qcom_phy_ctrl_rx_linecfg(phy, true);



		if (ufs_qcom_cap_qunipro(host)) {

			err = ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(

				hba);

			if (err)

				goto out;

		}

		/*

		 * Some UFS devices (and may be host) have issues if LCC is

		 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
@@ -520,7 +557,8 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 
			err = ufshcd_dme_set(hba,

					UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),

					0);



		if (err)

			goto out;

		break;

	case POST_CHANGE:

		ufs_qcom_link_startup_post_change(hba);
@@ -1382,12 +1420,22 @@ static void ufs_qcom_exit(struct ufs_hba *hba) 
}



static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,

						       u32 clk_cycles)

						       u32 clk_1us_cycles,

						       u32 clk_40ns_cycles)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	int err;

	u32 core_clk_ctrl_reg;

	u32 core_clk_ctrl_reg, clk_cycles;

	u32 mask = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;

	u32 offset = 0;



	/* Bits mask and offset changed on UFS host controller V4.0.0 onwards */

	if (host->hw_ver.major >= 4) {

		mask = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK_V4;

		offset = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_OFFSET_V4;

	}



	if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)

	if (clk_1us_cycles > mask)

		return -EINVAL;



	err = ufshcd_dme_get(hba,
@@ -1396,8 +1444,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 
	if (err)

		goto out;



	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;

	core_clk_ctrl_reg |= clk_cycles;

	core_clk_ctrl_reg &= ~mask;

	core_clk_ctrl_reg |= clk_1us_cycles;

	core_clk_ctrl_reg <<= offset;



	/* Clear CORE_CLK_DIV_EN */

	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
@@ -1405,25 +1454,83 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 
	err = ufshcd_dme_set(hba,

			     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),

			     core_clk_ctrl_reg);



	/* UFS host controller V4.0.0 onwards needs to program

	 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed frequency of

	 * unipro core clk of UFS host controller.

	 */

	if (!err && (host->hw_ver.major >= 4)) {

		if (clk_40ns_cycles > PA_VS_CORE_CLK_40NS_CYCLES_MASK)

			return -EINVAL;



		err = ufshcd_dme_get(hba,

				     UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES),

				     &clk_cycles);

		if (err)

			goto out;



		clk_cycles &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;

		clk_cycles |= clk_40ns_cycles;



		err = ufshcd_dme_set(hba,

				     UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES),

				     clk_cycles);

	}

out:

	return err;

}



static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)

static int ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(struct ufs_hba *hba)

{

	/* nothing to do as of now */

	return 0;

	struct ufs_clk_info *clki;

	struct list_head *head = &hba->clk_list_head;

	u32 max_freq = 0;

	int err = 0;



	list_for_each_entry(clki, head, list) {

		if (!IS_ERR_OR_NULL(clki->clk) &&

		    (!strcmp(clki->name, "core_clk_unipro"))) {

			max_freq = clki->max_freq;

			break;

		}

	}



static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)

	switch (max_freq) {

	case 300000000:

		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 300, 12);

		break;

	case 150000000:

		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150, 6);

		break;

	default:

		err = -EINVAL;

		break;

	}



	return err;

}



static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	struct ufs_pa_layer_attr *attr = &host->dev_req_params;

	int err = 0;



	if (!ufs_qcom_cap_qunipro(host))

		return 0;

		goto out;



	if (attr)

		__ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,

				      attr->hs_rate, false, true);



	/* set unipro core clock cycles to 150 and clear clock divider */

	return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);

	err = ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(hba);

out:

	return err;

}



static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)

{

	return 0;

}



static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
@@ -1454,12 +1561,40 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 
static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	struct ufs_pa_layer_attr *attr = &host->dev_req_params;

	int err = 0;

	struct ufs_clk_info *clki;

	struct list_head *head = &hba->clk_list_head;

	u32 curr_freq = 0;



	if (!ufs_qcom_cap_qunipro(host))

		return 0;



	/* set unipro core clock cycles to 75 and clear clock divider */

	return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);

	if (attr)

		ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,

				    attr->hs_rate, false);



	list_for_each_entry(clki, head, list) {

		if (!IS_ERR_OR_NULL(clki->clk) &&

		    (!strcmp(clki->name, "core_clk_unipro"))) {

			curr_freq = clk_get_rate(clki->clk);

			break;

		}

	}



	switch (curr_freq) {

	case 37500000:

		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 38, 2);

		break;

	case 75000000:

		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75, 3);

		break;

	default:

		err = -EINVAL;

		break;

	}



	return err;

}



static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,

drivers/scsi/ufs/ufs-qcom.h

+6 −0
Original line number Diff line number Diff line
@@ -138,6 +138,12 @@ enum { 
#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT		BIT(8)

#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	0xFF



#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK_V4	0xFFF

#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_OFFSET_V4	0x10



#define PA_VS_CORE_CLK_40NS_CYCLES	0x9007

#define PA_VS_CORE_CLK_40NS_CYCLES_MASK	0xF



static inline void

ufs_qcom_get_controller_revision(struct ufs_hba *hba,

				 u8 *major, u16 *minor, u16 *step)